公开(公告)号：US20190187218A1

公开(公告)日：2019-06-20

申请号：US16269331

申请日：2019-02-06

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Vratislav Michal ,  Michel Ayraud

IPC: G01R31/3835 ,  G01R31/36 ,  H03F3/45 ,  G01R1/30 ,  H03F1/02

CPC classification number: G01R31/3835 ,  G01R1/30 ,  G01R17/02 ,  G01R31/3646 ,  H03F1/0205 ,  H03F3/45179 ,  H03F3/45183 ,  H03F2200/129 ,  H03F2200/261 ,  H03F2200/471 ,  H03F2203/45151

Abstract: A circuit includes an amplifier having a first power terminal configured to be coupled to a supply voltage and a second power terminal configured to be coupled to a reference potential. The circuit further includes a first impedance element coupled between a first input terminal of the amplifier and a first output terminal of the amplifier. The circuit additionally includes a second impedance element coupled between the first input terminal and the reference potential. The amplifier is configured to output a first voltage at a second output terminal of the amplifier in response to the supply voltage being greater than an output voltage at the first output terminal of the amplifier. The amplifier is further configured to output a second voltage at the second output terminal of the amplifier in response to the supply voltage being less than the output voltage at the first output terminal of the amplifier.

公开(公告)号：US20190173426A1

公开(公告)日：2019-06-06

申请号：US16207696

申请日：2018-12-03

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Benoit MARCHAND ,  Francois DRUILHE

IPC: H03B5/36 ,  H03L7/099 ,  H03L7/183 ,  H03L1/02

Abstract: A quartz crystal resonator is connected to an array of switchable capacitors or resistors. The switched actuation of elements of the array is controlled by bits of a control word. At least one of the bits of the control word is controlled by pulse width modulation to effectuate a tuning of the oscillation frequency of the quartz crystal resonator.

公开(公告)号：US20190148334A1

公开(公告)日：2019-05-16

申请号：US16249122

申请日：2019-01-16

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： David AUCHERE ,  Asma HAJJI ,  Fabien QUERCIA ,  Jerome LOPEZ

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/552

Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.

公开(公告)号：US20190140176A1

公开(公告)日：2019-05-09

申请号：US16184246

申请日：2018-11-08

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck ARNAUD ,  David GALPIN ,  Stephane ZOLL ,  Olivier HINSINGER ,  Laurent FAVENNEC ,  Jean-Pierre ODDOU ,  Lucile BROUSSOUS ,  Philippe BOIVIN ,  Olivier WEBER ,  Philippe BRUN ,  Pierre MORIN

IPC: H01L45/00 ,  H01L27/24

Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.

公开(公告)号：US10267901B2

公开(公告)日：2019-04-23

申请号：US15169489

申请日：2016-05-31

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Marc Drader ,  Pascal Mellot

IPC: G01S7/486 ,  H01L27/144 ,  G01S17/10 ,  G01S17/36 ,  G01S7/487 ,  G01S7/491 ,  G01S7/493

Abstract: A ranging device includes an array of photon detection devices adapted to receive an optical signal reflected by an object in an image scene. First and second logic devices are adapted to respectively combine the outputs of first and second pluralities of the photon detection devices. A first range detection circuit is coupled to outputs of the first and second logic devices and a first counter is coupled to the output of the first logic device and adapted to generate a first pixel value by counting events generated by the first plurality of photon detection devices. A second counter is coupled to the output of the second logic device and is adapted to generate a second pixel value by counting events generated by the second plurality of photon detection devices. The first and second pixel values may be used in estimating a range to the object in the image scene.

公开(公告)号：US10257943B2

公开(公告)日：2019-04-09

申请号：US15926583

申请日：2018-03-20

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： David Auchere ,  Laurent Marechal

IPC: H05K1/18 ,  H05K3/42 ,  H01L23/64 ,  H01L23/498

Abstract: An electronic device includes a substrate having an external surface, and an integrated circuit over the external surface of the substrate. The substrate is provided with an electrical connection network including electrical links for linking the integrated circuit to another electrical device. Some of the electrical links include an impedance-compensating inductor on an external surface of the substrate.

公开(公告)号：US10229484B2

公开(公告)日：2019-03-12

申请号：US15365086

申请日：2016-11-30

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Grégory Roffet ,  Mathieu Thivin

IPC: G06T5/00 ,  H04N9/68 ,  G06T7/40 ,  G06T5/40 ,  H04N5/232 ,  H04N9/04

Abstract: Tone mapping is applied to pixels of a digital image. A luminance value of a pixel is determined based on whether one or more pixel intensity values of a pixel in a color space are within a pixel saturation range. A pixel gain is determined based on the determined luminance value of the pixel, and the determined pixel gain is applied to the pixel. The luminance value may also or instead be determined based on whether one or more of the pixel intensity values is within a pixel black-out range. A weight may be employed to determine the luminance value.

公开(公告)号：US10186466B2

公开(公告)日：2019-01-22

申请号：US15728969

申请日：2017-10-10

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Benoit Besancon ,  Luc Petit

IPC: H01L21/48 ,  H01L21/52 ,  H01L21/58 ,  H01L21/78 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498

Abstract: An electronic device includes a carrier substrate with at least one integrated-circuit chip mounted on a front face of the carrier substrate. An encapsulation block on the front face and embedding the integrated-circuit chip has a periphery with corners. The encapsulating block further has, in at least one local zone located in at least one corner and from the front face of the carrier substrate, a smaller thickness than a thickness of the encapsulation block at least in a surrounding zone. The electronic device is manufactured by a process in which the zone of smaller thickness is obtained by molding or by machining.

公开(公告)号：US20190007038A1

公开(公告)日：2019-01-03

申请号：US15946506

申请日：2018-04-05

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Vincent Binet ,  David Chesneau

IPC: H03K5/24 ,  H03K19/20 ,  H03F3/19

CPC classification number: H03K5/24 ,  H03F3/19 ,  H03K3/02337 ,  H03K5/1252 ,  H03K19/20 ,  H03K2005/00019

Abstract: A comparison circuit includes an input interface configured to receive input signals and an output interface configured to deliver an output signal. A comparator is coupled between the input interface and the output interface. An amplifier is coupled between the input interface and the comparator. A neutralization circuit is configured to neutralize any change of state of the output signal starting from each moment in time at which the change of state of the output signal occurs and lasting for a second duration of propagation that compensates for a duration of propagation of signals within the amplifier.

公开(公告)号：US10102171B2

公开(公告)日：2018-10-16

申请号：US15608857

申请日：2017-05-30

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics S.r.l.

Inventor： Daniele Mangano ,  Ignazio Antonino Urzi

IPC: G06F13/40 ,  G06F13/14 ,  G06F15/78

Abstract: A system, such as a System-on-Chip includes an interface component or PLUG which generates transactions over an IP block, such as an interconnect serving one or more clients via virtual channels. The client or clients are mapped onto the virtual channels via client/virtual channel mappings. The virtual channels are provided as a first set of virtual channels in the interface component which cooperate with a second set of virtual channels in the IP block. First and second client/virtual channel mappings for the first set of virtual channels and the second set of virtual channels are provided. The first and second client/virtual channel mappings are separately programmable and mutually decoupled from one another.