公开(公告)号：US20250095273A1

公开(公告)日：2025-03-20

申请号：US18509902

申请日：2023-11-15

Applicant: Apple Inc.

Inventor： Frank W. Liljeros ,  Karl D. Mann ,  Per Christian Corneliussen

IPC: G06T15/06 ,  G06T15/00

Abstract: Techniques are disclosed relating to memory page allocation for graphics processor. In some embodiments, a shader program includes a primary thread associated with ray tracing (that includes an instruction that indicates for the apparatus to launch one or more secondary threads). Memory resource allocator circuitry may receive a request to allocate a memory page in a page pool to a thread of the shader program, where the page pool includes a set of protected pages and a set of public pages. The allocator may allocate a page of the page pool to the requesting thread according to an allocation restriction, such that protected pages are allocable only to secondary threads that are launched based on a primary thread and public pages are allocable to both primary and secondary threads.

公开(公告)号：US20250094567A1

公开(公告)日：2025-03-20

申请号：US18510540

申请日：2023-11-15

Applicant: Apple Inc.

Inventor： John D Pape ,  Deepankar Duggal ,  Christopher M Tsay ,  Andrew H Lin ,  Corey C Stappenbeck

IPC: G06F21/54 ,  G06F21/55

Abstract: In an embodiment, a processor includes hardware circuitry which may be used to authenticate instruction operands. The processor may execute instructions that perform operand authentication both speculatively and non-speculatively. During speculative execution of such instructions, the processor may execute authentication such that no differences in observable state of the processor, relative to authentication result, are detectable via a side channel. During speculative execution, a result of authentication may be deferred until speculative execution of the instruction, and additional instructions, may be completed. Upon resolution of a condition that indicates acceptance of the speculative execution, a speculative execution result may cause a processor exception and stalling of execution at the instruction to be performed.

公开(公告)号：US20250094381A1

公开(公告)日：2025-03-20

申请号：US18959080

申请日：2024-11-25

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Andrew J. Beaumont-Smith ,  Boris S. Alvarez-Heredia ,  Pradeep Kanapathipillai ,  Ran A. Chachick

IPC: G06F15/80 ,  G06F7/544 ,  G06F7/57 ,  G06F9/30 ,  G06F9/38

Abstract: In an embodiment, a coprocessor may include a plurality of processing element circuits arranged in a first grid, where a given coprocessor instruction of an instruction set for the coprocessor is defined to cause evaluation of a second plurality of processing element circuits arranged in a second grid, where the second grid includes more processing element circuits than the first grid. The coprocessor may further include a scheduler circuit configured to issue instruction operations to the plurality of processing element circuits, where the scheduler circuit is configured to issue a given instruction operation corresponding to the given coprocessor instruction a plurality of times to complete the given coprocessor instruction, wherein different issuances of the given instruction operation are configured to cause respective different portions of the evaluation defined by the given coprocessor instruction to be performed.

公开(公告)号：US20250094357A1

公开(公告)日：2025-03-20

申请号：US18962158

申请日：2024-11-27

Applicant: Apple Inc.

Inventor： Jonathan M. Redshaw ,  Winnie W. Yeung ,  Benjiman L. Goodman ,  David K. Li ,  Zelin Zhang ,  Yoong Chert Foo

IPC: G06F12/126 ,  G06F12/0811 ,  G06F12/0891

Abstract: Techniques are disclosed relating to eviction control for cache lines that store register data. In some embodiments, memory hierarchy circuitry is configured to provide memory backing for register operand data in one or more cache circuits. Lock circuitry may control a first set of lock indicators for a set of registers for a first thread, including to assert one or more lock indicators for registers that are indicated, by decode circuitry, as being utilized by decoded instructions of the first thread. The lock circuitry may preserve register operand data in the one or more cache circuits, including to prevent eviction of a given cache line from a cache circuit based on an asserted lock indicator. The lock circuitry may clear the first set of lock indicators in response to a reset event. Disclosed techniques may advantageously retain relevant register information in the cache with limited control circuit area.

公开(公告)号：US20250094174A1

公开(公告)日：2025-03-20

申请号：US18783937

申请日：2024-07-25

Applicant: Apple Inc.

Inventor： Brandon H. Dwiel ,  Andrew J. Beaumont-Smith ,  Eric J. Furbish ,  John D. Pape ,  Stephen G. Meier ,  Tyler J. Huberty

IPC: G06F9/38

Abstract: A prefetcher for a coprocessor is disclosed. An apparatus includes a processor and a coprocessor that are configured to execute processor and coprocessor instructions, respectively. The processor and coprocessor instructions appear together in code sequences fetched by the processor, with the coprocessor instructions being provided to the coprocessor by the processor. The apparatus further includes a coprocessor prefetcher configured to monitor a code sequence fetched by the processor and, in response to identifying a presence of coprocessor instructions in the code sequence, capture the memory addresses, generated by the processor, of operand data for coprocessor instructions. The coprocessor is further configured to issue, for a cache memory accessible to the coprocessor, prefetches for data associated with the memory addresses prior to execution of the coprocessor instructions by the coprocessor.

公开(公告)号：US20250094093A1

公开(公告)日：2025-03-20

申请号：US18610974

申请日：2024-03-20

Applicant: Apple Inc.

Inventor： Eran Tamari ,  Brian S. Leibowitz

IPC: G06F3/06

Abstract: Techniques are disclosed relating to computing systems that use silicon photonics. In some embodiments, a computing system includes a plurality of compute die packages that include processors configured to execute program instructions that operate on data stored in a distributed memory accessible via a unified memory architecture. The computing system further includes a plurality of memory die packages configured to implement the unified memory architecture such that a given one of the memory die packages includes one or more optical interfaces configured to receive memory requests from the processors and one or more memory controllers configured to access a portion of the distributed memory in response to the received memory requests.

公开(公告)号：US20250093990A1

公开(公告)日：2025-03-20

申请号：US18969089

申请日：2024-12-04

Applicant: Apple Inc.

Inventor： Lejing Wang ,  Benjamin R. Blachnitzky ,  Lilli I. Jonsson ,  Nicolai Georg

IPC: G06F3/041 ,  G06F3/01 ,  G06F3/0488

Abstract: Detecting a touch includes receiving image data of a touching object of a user selecting selectable objects of a target surface, determining a rate of movement of the touching object, in response to determining that the rate of movement satisfies a predetermined threshold, modifying a touch detection parameter for detecting a touch event between the touching object and the target surface, and detecting one or more additional touch events using the modified touch detection parameter.

公开(公告)号：US20250093976A1

公开(公告)日：2025-03-20

申请号：US18969607

申请日：2024-12-05

Applicant: Apple Inc.

Inventor： Bart K. Andre ,  Brian T. Gleeson ,  Kristi E. Bauerly ,  William D. Lindmeier ,  Matthew J. Sundstrom ,  Geng Luo ,  Seung Wook Kim ,  Evangelos Christodoulou ,  Megan M. Sapp ,  Kainoa Kwon-Perez ,  David H. Bloom ,  Steven J. Taylor ,  John B. Morrell ,  Miao He ,  Hamza Kashif

IPC: G06F3/0354 ,  G01P13/00 ,  G01S5/30 ,  G06F3/01 ,  G06F3/0346 ,  G06F3/038 ,  G06F3/044 ,  G06F3/04815

Abstract: A computer input system includes a mouse including a housing having an interior surface defining an internal volume and a sensor assembly disposed in the internal volume. A processor is electrically coupled to the sensor assembly and a memory component having electronic instructions stored thereon that, when executed by the processor, causes the processor to determine an orientation of the mouse relative to a hand based on a touch input from the hand detected by the sensor assembly. The mouse can also have a circular array of touch sensors or lights that detect hand position and provide orientation information to the user.

公开(公告)号：US20250093646A1

公开(公告)日：2025-03-20

申请号：US18806514

申请日：2024-08-15

Applicant: Apple Inc.

Inventor： Pablo Benitez Gimenez ,  Julio Chaves ,  Dejan Grabovickic ,  Juan Carlos Minano Dominguez ,  Zachary A Granger

IPC: G02B27/01

Abstract: An electronic device may include a display with a display panel that emits light into an optical system. The system provides the light and world light to an eye box. The system may be implemented using a folded birdbath architecture. The system may include a partial reflector and a reflective polarizer in freeform curved rotationally asymmetric surfaces. The system may include two or three optical wedges. An air gap may separate two of the wedges. A quarter waveplate may be layered over the reflective polarizer and/or the partial reflector. A privacy filter may overlap the partial reflector. The wedges may perform total internal reflections on the light. The system may provide a horizontal field of view of the light to the eye box at a different point than a vertical field of view. A switchable shutter may overlap the system and may be synchronized to an external device display.

公开(公告)号：US20250093642A1

公开(公告)日：2025-03-20

申请号：US18798064

申请日：2024-08-08

Applicant: Apple Inc.

Inventor： Luis R. Deliz Centeno ,  Devin W. Chalmers

IPC: G02B27/00 ,  G02B27/01

Abstract: In a head-mounted device, position and motion sensors may be included to determine the orientation of the head-mounted device. A motion sensor may experience error that accumulates over time, sometimes referred to as drift. To mitigate the effect of drift in a motion sensor, a reference orientation for the motion sensor may be reset when a qualifying motion is detected. The qualifying motion may be detected using one or more criteria such as a total change in angular orientation or rate of change in angular orientation. The reference orientation for the motion sensor may also be reset when a duration of time elapses without a qualifying motion being detected.