公开(公告)号：US07214621B2

公开(公告)日：2007-05-08

申请号：US11131994

申请日：2005-05-18

Applicant: Hasan Nejad ,  Gordon A. Haller ,  Thomas Arthur Figura ,  Ravi Iyer

Inventor： Hasan Nejad ,  Gordon A. Haller ,  Thomas Arthur Figura ,  Ravi Iyer

IPC: H01L21/8244

CPC classification number: H01L27/10894 ,  H01L27/10876 ,  H01L27/10897 ,  Y10S439/917

Abstract: The invention includes methods of forming devices associated with semiconductor constructions. In exemplary methods, common processing steps are utilized to form fully silicided recessed array access gates and partially silicided periphery transistor gates.

Abstract translation: 本发明包括形成与半导体结构相关的器件的方法。 在示例性方法中，利用通常的处理步骤来形成完全硅化的凹陷阵列存取栅极和部分硅化的外围晶体管栅极。

公开(公告)号：US07209378B2

公开(公告)日：2007-04-24

申请号：US10925243

申请日：2004-08-25

Applicant: Hasan Nejad ,  Mirmajid Seyyedy

Inventor： Hasan Nejad ,  Mirmajid Seyyedy

IPC: G11C11/00

CPC classification number: G11C11/16 ,  G11C5/02 ,  G11C11/22 ,  G11C13/0011 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/71 ,  H01L27/228 ,  H01L27/24

Abstract: A memory array architecture incorporates certain advantages from both cross-point and 1T-1Cell architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of memory cells, each column being provided in a respective stacked memory layer.

Abstract translation: 存储器阵列架构在读取操作期间融合了交叉点和1T-1Cell架构的某些优点。 通过使用单个存取晶体管来控制多个堆叠列的存储单元的读取，利用了1T-1Cell架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度 列设置在相应的堆叠存储层中。

公开(公告)号：US20070020774A1

公开(公告)日：2007-01-25

申请号：US11521289

申请日：2006-09-13

Applicant: Hasan Nejad

Inventor： Hasan Nejad

IPC: H01L21/00

CPC classification number: H01L27/222 ,  G11C11/16

Abstract: The invention includes a method of forming a magnetoresistive memory device having a memory bit stack. The stack includes a first magnetic layer, a second magnetic layer, and a non-magnetic layer between the first and second magnetic layers. A first conductive line is proximate the stack and configured for utilization in reading information from the memory bit. The first conductive line is ohmically connecting with either the first or second magnetic layer. A second conductive line is spaced from the stack by a sufficient distance that the second conductive line is not ohmically connected to the stack, and is configured for utilization in writing information to the memory bit. The invention also includes methods of storing and retrieving information.

Abstract translation: 本发明包括形成具有存储器位堆栈的磁阻存储器件的方法。 该堆叠包括在第一和第二磁性层之间的第一磁性层，第二磁性层和非磁性层。 第一导线靠近堆叠并被配置为用于从存储器位读取信息。 第一导线与第一或第二磁性层的欧姆连接。 第二导线与叠层隔开足够的距离，使得第二导线不被欧姆连接到堆叠，并被配置为用于将信息写入存储器位。 本发明还包括存储和检索信息的方法。

公开(公告)号：US20060171224A1

公开(公告)日：2006-08-03

申请号：US11394233

申请日：2006-03-31

Applicant: Hasan Nejad ,  Mirmajid Seyyedy

Inventor： Hasan Nejad ,  Mirmajid Seyyedy

IPC: G11C7/00

CPC classification number: G11C11/16 ,  G11C5/02 ,  G11C11/22 ,  G11C13/0011 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/71 ,  H01L27/228 ,  H01L27/24

Abstract: A memory array architecture incorporates certain advantages from both cross-point and 1T-1Cell architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of memory cells, each column being provided in a respective stacked memory layer.

Abstract translation: 存储器阵列架构在读取操作期间融合了交叉点和1T-1Cell架构的某些优点。 通过使用单个存取晶体管来控制多个堆叠列的存储单元的读取，利用了1T-1Cell架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度 列设置在相应的堆叠存储层中。

公开(公告)号：US20050226038A1

公开(公告)日：2005-10-13

申请号：US11142448

申请日：2005-06-02

Applicant: Hasan Nejad ,  Mirmajid Seyyedy

Inventor： Hasan Nejad ,  Mirmajid Seyyedy

IPC: G11C11/00 ,  G11C11/16

CPC classification number: H01L27/228 ,  G11C5/02 ,  G11C11/16

Abstract: This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of MRAM cells each column being provided in a respective stacked memory layer.

Abstract translation: 本发明涉及一种在读取操作期间结合来自交叉点和1T-1MTJ架构的某些优点的MRAM阵列体系结构。 通过使用单个存取晶体管来控制1T-1MTJ架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度，以控制每个列的多个堆叠列的MRAM单元的读数 设置在相应的堆叠存储层中。

公开(公告)号：US06882553B2

公开(公告)日：2005-04-19

申请号：US10214167

申请日：2002-08-08

Applicant: Hasan Nejad ,  Mirmajid Seyyedy

Inventor： Hasan Nejad ,  Mirmajid Seyyedy

IPC: G11C11/00 ,  G11C11/16 ,  G11C7/00

CPC classification number: H01L27/228 ,  G11C5/02 ,  G11C11/16

Abstract: This invention relates to a resistive memory array architecture which incorporates certain advantages from both cross-point and one transistor per cell architectures during reading operations. The fast read-time and higher signal to noise ratio of the one transistor per cell architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of resistive memory cells each column being provided in a respective stacked memory layer.

Abstract translation: 本发明涉及一种电阻存储器阵列架构，其结合了在读取操作期间每个单元结构的交叉点和一个晶体管的某些优点。 通过使用单个存取晶体管来控制多个堆叠列的电阻存储器单元的读取，都利用了每个单元架构的一个晶体管的快速读取时间和更高的信噪比以及交叉点架构的较高的堆积密度 每列设置在相应的堆叠存储层中。

公开(公告)号：US06780654B2

公开(公告)日：2004-08-24

申请号：US10321165

申请日：2002-12-16

Applicant: Hasan Nejad ,  James G. Deak

Inventor： Hasan Nejad ,  James G. Deak

IPC: H01L2100

CPC classification number: H01L27/222

Abstract: The invention includes a construction comprising an MRAM device between a pair of conductive lines. Each of the conductive lines can generate a magnetic field encompassing at least a portion of the MRAM device. Each of the conductive lines is surrounded on three sides by magnetic material to concentrate the magnetic fields generated by the conductive lines at the MRAM device. The invention also includes a method of forming an assembly containing MRAM devices. A plurality of MRAM devices are formed over a substrate. An electrically conductive material is formed over the MRAM devices, and patterned into a plurality of lines. The lines are in a one-to-one correspondence with the MRAM devices and are spaced from one another. After the conductive material is patterned into lines, a magnetic material is formed to extend over the lines and within spaces between the lines.

Abstract translation: 本发明包括在一对导线之间包括MRAM器件的结构。 每个导线可以产生包围MRAM装置的至少一部分的磁场。 每个导线在三面被磁性材料包围以将由导线产生的磁场集中在MRAM器件上。 本发明还包括形成包含MRAM器件的组件的方法。 在衬底上形成多个MRAM器件。 导电材料形成在MRAM器件上，并被图案化成多条线。 这些线与MRAM器件一一对应，并且彼此间隔开。 在将导电材料图案化成线之后，形成磁性材料以在线之间和线之间的空间内延伸。