公开(公告)号：US07440318B2

公开(公告)日：2008-10-21

申请号：US12021729

申请日：2008-01-29

申请人： Yupin Fong ,  Jun Wan ,  Jeffrey Lutze

发明人： Yupin Fong ,  Jun Wan ,  Jeffrey Lutze

IPC分类号： G11C11/34

CPC分类号： G11C16/3418 ,  G11C16/3427

摘要： A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.

摘要翻译： 公开了一种用于减少或去除非易失性存储设备中的读取干扰形式的系统。 一个实施例旨在通过消除或最小化存储器元件的通道的升高来防止读取干扰。 例如，一个实施方式在读取过程期间防止或减少NAND串通道的源极侧的升压。 因为NAND串通道的源极侧不被提升，所以读取干扰的至少一种形式被最小化或不发生。

公开(公告)号：US20080151627A1

公开(公告)日：2008-06-26

申请号：US11614879

申请日：2006-12-21

申请人： Dana Lee ,  Jeffrey Lutze

发明人： Dana Lee ,  Jeffrey Lutze

IPC分类号： G11C16/04

CPC分类号： G11C16/3418

摘要： A low voltage method of programming a selected non-volatile memory cell in a memory array having a gate node coupled to a wordline WL(n) and a drain node connected to a selected bitline by injecting hot carriers from a drain region of an injecting memory cell having a gate node coupled to a next neighbor wordline WL(n-1) into a floating gate of the selected non-volatile memory cell on the wordline WL(n).

摘要翻译： 一种低电压方法，通过从注入存储器的漏极区域注入热载流子来对存储器阵列中的所选择的非易失性存储单元进行编程，所述存储器阵列具有耦合到字线WL（n）的栅极节点和连接到选定位线的漏极节点 小区具有耦合到下一个相邻字线WL（n-1）的门节点到位于字线WL（n）上的所选择的非易失性存储器单元的浮动栅极。

公开(公告)号：US20080137423A1

公开(公告)日：2008-06-12

申请号：US12021729

申请日：2008-01-29

申请人： Yupin Fong ,  Jun Wan ,  Jeffrey Lutze

发明人： Yupin Fong ,  Jun Wan ,  Jeffrey Lutze

IPC分类号： G11C16/06

CPC分类号： G11C16/3418 ,  G11C16/3427

摘要： A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.

公开(公告)号：US20080019180A1

公开(公告)日：2008-01-24

申请号：US11866261

申请日：2007-10-02

申请人： Jun Wan ,  Jeffrey Lutze ,  Masaaki Higashitani ,  Gerrit Hemink ,  Ken Oowada ,  Jian Chen ,  Geoffrey Gongwer

发明人： Jun Wan ,  Jeffrey Lutze ,  Masaaki Higashitani ,  Gerrit Hemink ,  Ken Oowada ,  Jian Chen ,  Geoffrey Gongwer

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3418

摘要： A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.

摘要翻译： 编程非易失性存储器系统以减少或避免编程干扰。 根据一个实施例，对于单个非易失性存储器系统采用多个程序禁止方案。 基于正在编程的字线选择程序禁止方案。 已经发现某些程序禁止方案能够更好地最小化或消除选择字线上的程序干扰。 在一个实施例中，选择编程禁止方案包括选择编程电压脉冲斜率。 在应用于选择字线时，已经发现了不同的斜率以更好地最小化程序干扰。 在另一个实施例中，在程序操作之前或期间检测存储器系统的温度。 可以基于系统的温度来选择程序禁止方案。

公开(公告)号：US07295478B2

公开(公告)日：2007-11-13

申请号：US11127743

申请日：2005-05-12

申请人： Jun Wan ,  Jeffrey Lutze ,  Masaaki Higashitani ,  Gerrit Jan Hemink ,  Ken Oowada ,  Jian Chen ,  Geoffrey S. Gongwer

发明人： Jun Wan ,  Jeffrey Lutze ,  Masaaki Higashitani ,  Gerrit Jan Hemink ,  Ken Oowada ,  Jian Chen ,  Geoffrey S. Gongwer

IPC分类号： G11C7/00

CPC分类号： G11C16/3418

摘要： A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.

摘要翻译： 编程非易失性存储器系统以减少或避免编程干扰。 根据一个实施例，对于单个非易失性存储器系统采用多个程序禁止方案。 基于正在编程的字线选择程序禁止方案。 已经发现某些程序禁止方案能够更好地最小化或消除选择字线上的程序干扰。 在一个实施例中，选择编程禁止方案包括选择编程电压脉冲斜率。 在应用于选择字线时，已经发现了不同的斜率以更好地最小化程序干扰。 在另一个实施例中，在程序操作之前或期间检测存储器系统的温度。 可以基于系统的温度来选择程序禁止方案。

公开(公告)号：US20070252192A1

公开(公告)日：2007-11-01

申请号：US11775808

申请日：2007-07-10

申请人： Nima Mokhlesi ,  Jeffrey Lutze

发明人： Nima Mokhlesi ,  Jeffrey Lutze

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11521 ,  G11C16/0458 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7883

摘要： An array of a pillar-type nonvolatile memory cells (803) has each memory cell isolated from adjacent memory cells by a trench (810). Each memory cell is formed by a stacking process layers on a substrate: tunnel oxide layer (815), polysilicon floating gate layer (819), ONO or oxide layer (822), polysilicon control gate layer (825). Many aspects of the process are self-aligned. An array of these memory cells will require less segmentation. Furthermore, the memory cell has enhanced programming characteristics because electrons are directed at a normal or nearly normal angle (843) to the floating gate (819).

摘要翻译： 柱状非易失性存储单元（803）的阵列具有通过沟槽（810）与相邻存储单元隔离的每个存储单元。 每个存储单元由衬底上的堆叠处理层形成：隧道氧化物层（815），多晶硅浮动栅极层（819），ONO或氧化物层（822），多晶硅控制栅极层（825）。 这个过程的很多方面都是自相矛盾的。 这些存储单元的阵列将需要较少的分割。 此外，存储单元具有增强的编程特性，因为电子被引导到浮动栅极（819）的正常或几乎正常的角度（843）。

公开(公告)号：US20070127291A1

公开(公告)日：2007-06-07

申请号：US11296087

申请日：2005-12-06

申请人： Yupin Fong ,  Jun Wan ,  Jeffrey Lutze

发明人： Yupin Fong ,  Jun Wan ,  Jeffrey Lutze

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3427

摘要： A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.

公开(公告)号：US20070025157A1

公开(公告)日：2007-02-01

申请号：US11194439

申请日：2005-08-01

申请人： Jun Wan ,  Jeffrey Lutze

发明人： Jun Wan ,  Jeffrey Lutze

IPC分类号： G11C11/34 ,  G11C16/06 ,  G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： The maximum allowable number of voltage programming pulses to program memory elements of a non-volatile memory device is adjusted to account for changes in the memory elements which occur over time. Programming pulses are applied until the threshold voltage of one or more memory elements reaches a certain verify level, after which a defined maximum number of additional pulses may be applied to other memory elements to allow them to also reach associated target threshold voltage levels. The technique enforces a maximum allowable number of programming pulses that can change over time as the memory is cycled.

摘要翻译： 调整非易失性存储器件对程序存储器元件的电压编程脉冲的最大允许数量，以便考虑随时间发生的存储元件的变化。 施加编程脉冲，直到一个或多个存储器元件的阈值电压达到某个验证电平，之后可以将限定的最大数量的附加脉冲施加到其它存储器元件以允许它们也达到相关联的目标阈值电压电平。 该技术实现了随着存储器循环而随时间变化的最大允许编程脉冲数。

公开(公告)号：US20060279990A1

公开(公告)日：2006-12-14

申请号：US11127743

申请日：2005-05-12

申请人： Jun Wan ,  Jeffrey Lutze ,  Masaaki Higashitani ,  Gerrit Hemink ,  Ken Oowada ,  Jian Chen ,  Geoffrey Gongwer

发明人： Jun Wan ,  Jeffrey Lutze ,  Masaaki Higashitani ,  Gerrit Hemink ,  Ken Oowada ,  Jian Chen ,  Geoffrey Gongwer

IPC分类号： G11C16/04

CPC分类号： G11C16/3418

摘要： A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.

摘要翻译： 编程非易失性存储器系统以减少或避免编程干扰。 根据一个实施例，对于单个非易失性存储器系统采用多个程序禁止方案。 基于正在编程的字线选择程序禁止方案。 已经发现某些程序禁止方案能够更好地最小化或消除选择字线上的程序干扰。 在一个实施例中，选择编程禁止方案包括选择编程电压脉冲斜率。 在应用于选择字线时，已经发现了不同的斜率以更好地最小化程序干扰。 在另一个实施例中，在程序操作之前或期间检测存储器系统的温度。 可以基于系统的温度来选择程序禁止方案。

公开(公告)号：US20060202258A1

公开(公告)日：2006-09-14

申请号：US11435456

申请日：2006-05-16

申请人： Nima Mokhlesi ,  Jeffrey Lutze

发明人： Nima Mokhlesi ,  Jeffrey Lutze

IPC分类号： H01L29/788

CPC分类号： H01L27/11 ,  H01L21/28273 ,  H01L21/823437 ,  H01L27/1104 ,  H01L27/115 ,  Y10S257/903

摘要： Various techniques are described which utilize multiple poly-silicon layers in the design and fabrication of various logic elements that are used in semiconductor devices. According to a specific implementation of the present invention, logic gate cell sizes and memory array cell sizes may be reduced by fabricating various transistor gates using multiple poly-silicon layers. The techniques of the present invention of using multiple layers of poly-silicon to form transistor gates of logic elements provides extra degrees of freedom in fine tuning transistor parameters such as, for example, oxide thickness, threshold voltage, maximum allowed gate voltage, etc.

摘要翻译： 描述了在半导体器件中使用的各种逻辑元件的设计和制造中利用多个多晶硅层的各种技术。 根据本发明的具体实现，可以通过使用多个多晶硅层制造各种晶体管栅极来减小逻辑门单元尺寸和存储器阵列单元尺寸。 使用多层多晶硅形成逻辑元件的晶体管栅极的本发明的技术在微调晶体管参数例如氧化物厚度，阈值电压，最大允许栅极电压等中提供了额外的自由度。