公开(公告)号：US20070147113A1

公开(公告)日：2007-06-28

申请号：US11321996

申请日：2005-12-28

申请人： Nima Mokhlesi ,  Jeffrey Lutze

发明人： Nima Mokhlesi ,  Jeffrey Lutze

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C11/34

CPC分类号： G11C16/28

摘要： The present invention presents a scheme for sensing memory cells. Selected memory cells are discharged through their channels to ground and then have a voltage level placed on the traditional source and another voltage level placed on the control gate, and allowing the cell bit line to charge up. The bit line of the memory cell will then charge up until the bit line voltage becomes sufficiently high to shut off any further cell conduction. The rise of the bit line voltage will occur at a rate and to a level dependent upon the data state of the cell, and the cell will then shut off when the bit line reaches a high enough level such that the body effect affected memory cell threshold is reached, at which point the current essentially shuts off. A particular embodiment performs multiple such sensing sub-operations, each with a different control gate voltage, but with multiple states being sensed in each operation by charging the previously discharged cells up through their source.

摘要翻译： 本发明提供了一种用于感测存储器单元的方案。 所选择的存储单元通过其通道放电到地，然后将电压电平放置在传统源上，并将另一个电压电平放置在控制栅上，并允许单元位线充电。 存储单元的位线然后将充电直到位线电压变得足够高以截止任何进一步的单元导通。 位线电压的升高将以一定的速率发生，并且取决于单元的数据状态，并且当位线达到足够高的电平时，单元将关闭，使得体效应影响存储单元阈值 到达目前，当前基本上关闭。 特定实施例执行多个这样的感测子操作，每个具有不同的控制栅极电压，但是在每个操作中通过对先前放电的单元通过其源极充电来感测多个状态。

公开(公告)号：US20070023838A1

公开(公告)日：2007-02-01

申请号：US11540262

申请日：2006-09-29

申请人： Nima Mokhlesi ,  Jeffrey Lutze

发明人： Nima Mokhlesi ,  Jeffrey Lutze

IPC分类号： H01L27/12

CPC分类号： H01L27/11 ,  H01L21/28273 ,  H01L21/823437 ,  H01L27/1104 ,  H01L27/115 ,  Y10S257/903

摘要： Various embodiments are directed to different methods and systems relating to design and implementation of memory cells such as, for example, static random access memory (SRAM) cells. In one embodiment, a memory cell may include a first layer of conductive material and a second layer of conductive material. The first layer may include a first gate region and a first interconnect region, and the second layer of conductive material may include a second gate region and a second interconnect region. It will be appreciated that the various techniques described herein for using multiple layers of conductive material to form interconnect regions and/or gate regions of memory cells provides extra degrees of freedom in fine tuning memory cell parameters such as, for example, oxide thickness, threshold voltage, maximum allowed gate voltage, etc.

摘要翻译： 各种实施例涉及与诸如静态随机存取存储器（SRAM）单元等存储单元的设计和实现有关的不同方法和系统。 在一个实施例中，存储单元可以包括第一导电材料层和第二导电材料层。 第一层可以包括第一栅极区和第一互连区，并且第二层导电材料可以包括第二栅极区和第二互连区。 应当理解，本文描述的用于使用多层导电材料形成存储器单元的互连区域和/或栅极区域的各种技术在微调存储器单元参数中提供了额外的自由度，例如，氧化物厚度，阈值 电压，最大允许栅极电压等

公开(公告)号：US20050157549A1

公开(公告)日：2005-07-21

申请号：US10762181

申请日：2004-01-21

申请人： Nima Mokhlesi ,  Jeffrey Lutze

发明人： Nima Mokhlesi ,  Jeffrey Lutze

IPC分类号： G11C16/04 ,  H01L21/336 ,  H01L21/8247 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/7881

摘要： A non-volatile memory device has a channel region between source/drain regions, a floating gate, a control gate, a first dielectric region between the channel region and the floating gate, and a second dielectric region between the floating gate and the control gate. The first dielectric region includes a high-K material. The non-volatile memory device is programmed and/or erased by transferring charge between the floating gate and the control gate via the second dielectric region.

摘要翻译： 非易失性存储器件在源极/漏极区域之间具有沟道区域，浮置栅极，控制栅极，沟道区域和浮置栅极之间的第一介电区域以及浮置栅极和控制栅极之间的第二介电区域 。 第一电介质区域包括高K材料。 通过经由第二电介质区域在浮动栅极和控制栅极之间传送电荷来对非易失性存储器件进行编程和/或擦除。

公开(公告)号：US20070252192A1

公开(公告)日：2007-11-01

申请号：US11775808

申请日：2007-07-10

申请人： Nima Mokhlesi ,  Jeffrey Lutze

发明人： Nima Mokhlesi ,  Jeffrey Lutze

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11521 ,  G11C16/0458 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7883

摘要： An array of a pillar-type nonvolatile memory cells (803) has each memory cell isolated from adjacent memory cells by a trench (810). Each memory cell is formed by a stacking process layers on a substrate: tunnel oxide layer (815), polysilicon floating gate layer (819), ONO or oxide layer (822), polysilicon control gate layer (825). Many aspects of the process are self-aligned. An array of these memory cells will require less segmentation. Furthermore, the memory cell has enhanced programming characteristics because electrons are directed at a normal or nearly normal angle (843) to the floating gate (819).

摘要翻译： 柱状非易失性存储单元（803）的阵列具有通过沟槽（810）与相邻存储单元隔离的每个存储单元。 每个存储单元由衬底上的堆叠处理层形成：隧道氧化物层（815），多晶硅浮动栅极层（819），ONO或氧化物层（822），多晶硅控制栅极层（825）。 这个过程的很多方面都是自相矛盾的。 这些存储单元的阵列将需要较少的分割。 此外，存储单元具有增强的编程特性，因为电子被引导到浮动栅极（819）的正常或几乎正常的角度（843）。

公开(公告)号：US20060202258A1

公开(公告)日：2006-09-14

申请号：US11435456

申请日：2006-05-16

申请人： Nima Mokhlesi ,  Jeffrey Lutze

发明人： Nima Mokhlesi ,  Jeffrey Lutze

IPC分类号： H01L29/788

CPC分类号： H01L27/11 ,  H01L21/28273 ,  H01L21/823437 ,  H01L27/1104 ,  H01L27/115 ,  Y10S257/903

摘要： Various techniques are described which utilize multiple poly-silicon layers in the design and fabrication of various logic elements that are used in semiconductor devices. According to a specific implementation of the present invention, logic gate cell sizes and memory array cell sizes may be reduced by fabricating various transistor gates using multiple poly-silicon layers. The techniques of the present invention of using multiple layers of poly-silicon to form transistor gates of logic elements provides extra degrees of freedom in fine tuning transistor parameters such as, for example, oxide thickness, threshold voltage, maximum allowed gate voltage, etc.

摘要翻译： 描述了在半导体器件中使用的各种逻辑元件的设计和制造中利用多个多晶硅层的各种技术。 根据本发明的具体实现，可以通过使用多个多晶硅层制造各种晶体管栅极来减小逻辑门单元尺寸和存储器阵列单元尺寸。 使用多层多晶硅形成逻辑元件的晶体管栅极的本发明的技术在微调晶体管参数例如氧化物厚度，阈值电压，最大允许栅极电压等中提供了额外的自由度。

公开(公告)号：US07064034B2

公开(公告)日：2006-06-20

申请号：US10211433

申请日：2002-08-02

申请人： Nima Mokhlesi ,  Jeffrey Lutze

发明人： Nima Mokhlesi ,  Jeffrey Lutze

IPC分类号： H01L21/8234 ,  H01L21/8236

CPC分类号： H01L27/11 ,  H01L21/28273 ,  H01L21/823437 ,  H01L27/1104 ,  H01L27/115 ,  Y10S257/903

摘要： Various techniques are described which utilize multiple poly-silicon layers in the design and fabrication of various logic elements that are used in semiconductor devices. According to a specific implementation of the present invention, logic gate cell sizes and memory array cell sizes may be reduced by fabricating various transistor gates using multiple poly-silicon layers. The techniques of the present invention of using multiple layers of poly-silicon to form transistor gates of logic elements provides extra degrees of freedom in fine tuning transistor parameters such as, for example, oxide thickness, threshold voltage, maximum allowed gate voltage, etc.

公开(公告)号：US07265423B2

公开(公告)日：2007-09-04

申请号：US11435456

申请日：2006-05-16

申请人： Nima Mokhlesi ,  Jeffrey Lutze

发明人： Nima Mokhlesi ,  Jeffrey Lutze

IPC分类号： H01L29/76

CPC分类号： H01L27/11 ,  H01L21/28273 ,  H01L21/823437 ,  H01L27/1104 ,  H01L27/115 ,  Y10S257/903

摘要： Various techniques are described which utilize multiple poly-silicon layers in the design and fabrication of various logic elements that are used in semiconductor devices. According to a specific implementation of the present invention, logic gate cell sizes and memory array cell sizes may be reduced by fabricating various transistor gates using multiple poly-silicon layers. The techniques of the present invention of using multiple layers of poly-silicon to form transistor gates of logic elements provides extra degrees of freedom in fine tuning transistor parameters such as, for example, oxide thickness, threshold voltage, maximum allowed gate voltage, etc.

摘要翻译： 描述了在半导体器件中使用的各种逻辑元件的设计和制造中利用多个多晶硅层的各种技术。 根据本发明的具体实现，可以通过使用多个多晶硅层制造各种晶体管栅极来减小逻辑门单元尺寸和存储器阵列单元尺寸。 使用多层多晶硅形成逻辑元件的晶体管栅极的本发明的技术在微调晶体管参数例如氧化物厚度，阈值电压，最大允许栅极电压等中提供了额外的自由度。

公开(公告)号：US20050127428A1

公开(公告)日：2005-06-16

申请号：US10732967

申请日：2003-12-10

申请人： Nima Mokhlesi ,  Jeffrey Lutze

发明人： Nima Mokhlesi ,  Jeffrey Lutze

IPC分类号： G11C16/04 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0458 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7883

摘要： An array of a pillar-type nonvolatile memory cells (803) has each memory cell isolated from adjacent memory cells by a trench (810). Each memory cell is formed by a stacking process layers on a substrate: tunnel oxide layer (815), polysilicon floating gate layer (819), ONO or oxide layer (822), polysilicon control gate layer (825). Many aspects of the process are self-aligned. An array of these memory cells will require less segmentation. Furthermore, the memory cell has enhanced programming characteristics because electrons are directed at a normal or nearly normal angle (843) to the floating gate (819).

摘要翻译： 柱状非易失性存储单元（803）的阵列具有通过沟槽（810）与相邻存储单元隔离的每个存储单元。 每个存储单元由衬底上的堆叠处理层形成：隧道氧化物层（815），多晶硅浮动栅极层（819），ONO或氧化物层（822），多晶硅控制栅极层（825）。 这个过程的很多方面都是自相矛盾的。 这些存储单元的阵列将需要较少的分割。 此外，存储单元具有增强的编程特性，因为电子被引导到浮动栅极（819）的正常或几乎正常的角度（843）。

公开(公告)号：US07425744B2

公开(公告)日：2008-09-16

申请号：US11540262

申请日：2006-09-29

申请人： Nima Mokhlesi ,  Jeffrey Lutze

发明人： Nima Mokhlesi ,  Jeffrey Lutze

IPC分类号： H01L27/12

CPC分类号： H01L27/11 ,  H01L21/28273 ,  H01L21/823437 ,  H01L27/1104 ,  H01L27/115 ,  Y10S257/903

摘要： Various embodiments are directed to different methods and systems relating to design and implementation of memory cells such as, for example, static random access memory (SRAM) cells. In one embodiment, a memory cell may include a first layer of conductive material and a second layer of conductive material. The first layer may include a first gate region and a first interconnect region, and the second layer of conductive material may include a second gate region and a second interconnect region. It will be appreciated that the various techniques described herein for using multiple layers of conductive material to form interconnect regions and/or gate regions of memory cells provides extra degrees of freedom in fine tuning memory cell parameters such as, for example, oxide thickness, threshold voltage, maximum allowed gate voltage, etc.

摘要翻译： 各种实施例涉及与诸如静态随机存取存储器（SRAM）单元等存储单元的设计和实现有关的不同方法和系统。 在一个实施例中，存储单元可以包括第一导电材料层和第二导电材料层。 第一层可以包括第一栅极区域和第一互连区域，并且第二层导电材料可以包括第二栅极区域和第二互连区域。 应当理解，本文描述的用于使用多层导电材料形成存储器单元的互连区域和/或栅极区域的各种技术在微调存储器单元参数中提供了额外的自由度，例如，氧化物厚度，阈值 电压，最大允许栅极电压等

公开(公告)号：US20070025145A1

公开(公告)日：2007-02-01

申请号：US11470932

申请日：2006-09-07

申请人： Nima Mokhlesi ,  Jeffrey Lutze

发明人： Nima Mokhlesi ,  Jeffrey Lutze

IPC分类号： G11C16/04

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/7881

摘要： A non-volatile memory device has a channel region between source/drain regions, a floating gate, a control gate, a first dielectric region between the channel region and the floating gate, and a second dielectric region between the floating gate and the control gate. The first dielectric region includes a high-K material. The non-volatile memory device is programmed and/or erased by transferring charge between the floating gate and the control gate via the second dielectric region.

摘要翻译： 非易失性存储器件在源极/漏极区域之间具有沟道区域，浮置栅极，控制栅极，沟道区域和浮置栅极之间的第一介电区域以及浮置栅极和控制栅极之间的第二介电区域 。 第一电介质区域包括高K材料。 通过经由第二电介质区域在浮动栅极和控制栅极之间传送电荷来对非易失性存储器件进行编程和/或擦除。