公开(公告)号：US20100020613A1

公开(公告)日：2010-01-28

申请号：US12572069

申请日：2009-10-01

申请人： Jeffrey Lutze

发明人： Jeffrey Lutze

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/12 ,  G11C16/0483

摘要： A system is disclosed for programming non-volatile storage that improves performance by setting the starting programming voltage to a first level for fresh parts and adjusting the starting programming voltage as the memory is cycled. For example, the system programs a set of non-volatile storage elements during a first period using an increasing program signal with a first initial value and subsequently programs the set of non-volatile storage elements during a second period using an increasing program signal with a second initial value, where the second period is subsequent to the first period and the second initial value is different than the first initial value.

摘要翻译： 公开了一种用于编程非易失性存储器的系统，其通过将起始编程电压设置为新鲜部件的第一电平并在存储器循环时调整起始编程电压来提高性能。 例如，该系统使用具有第一初始值的增加的程序信号在第一时段期间对一组非易失性存储元件进行编程，并且随后使用增加的程序信号在第二周期期间对该组非易失性存储元件进行编程， 第二初始值，其中第二周期在第一周期之后且第二初始值不同于第一初始值。

公开(公告)号：US07633812B2

公开(公告)日：2009-12-15

申请号：US12018275

申请日：2008-01-23

申请人： Jeffrey Lutze

发明人： Jeffrey Lutze

IPC分类号： G11C16/04

CPC分类号： G11C16/12 ,  G11C16/0483

摘要： A system is disclosed for programming non-volatile storage that improves performance by setting the starting programming voltage to a first level for fresh parts and adjusting the starting programming voltage as the memory is cycled. For example, the system programs a set of non-volatile storage elements during a first period using an increasing program signal with a first initial value and subsequently programs the set of non-volatile storage elements during a second period using an increasing program signal with a second initial value, where the second period is subsequent to the first period and the second initial value is different than the first initial value.

摘要翻译： 公开了一种用于编程非易失性存储器的系统，其通过将起始编程电压设置为新鲜部件的第一电平并在存储器循环时调整起始编程电压来提高性能。 例如，该系统使用具有第一初始值的增加的程序信号在第一时段期间对一组非易失性存储元件进行编程，并且随后使用增加的程序信号在第二周期期间对该组非易失性存储元件进行编程， 第二初始值，其中第二周期在第一周期之后且第二初始值不同于第一初始值。

公开(公告)号：US20080151628A1

公开(公告)日：2008-06-26

申请号：US11614884

申请日：2006-12-21

申请人： Dana Lee ,  Jeffrey Lutze

发明人： Dana Lee ,  Jeffrey Lutze

IPC分类号： G11C16/10

CPC分类号： G11C16/0483 ,  G11C16/10

摘要： System for programming a selected non-volatile memory cell in a memory array having a gate node coupled to a wordline WL(n) and a drain node connected to a selected bitline by injecting hot carriers from a drain region of an injecting memory cell having a gate node coupled to a next neighbor wordline WL(n−1) into a floating gate of the selected non-volatile memory cell on the wordline WL(n).

摘要翻译： 用于通过从注入存储器单元的漏极区域注入热载流子来对存储器阵列中的所选择的非易失性存储单元进行编程的系统，所述存储器阵列具有耦合到字线WL（n）的栅极节点和连接到所选位线的漏极节点 门节点与下一个相邻字线WL（n-1）耦合到字线WL（n）上的所选择的非易失性存储器单元的浮动栅极。

公开(公告)号：US20080137431A1

公开(公告)日：2008-06-12

申请号：US12018279

申请日：2008-01-23

申请人： Jeffrey Lutze

发明人： Jeffrey Lutze

IPC分类号： G11C16/06

CPC分类号： G11C16/12 ,  G11C16/0483

摘要： A system is disclosed for programming non-volatile storage that improves performance by setting the starting programming voltage to a first level for fresh parts and adjusting the starting programming voltage as the memory is cycled. For example, the system programs a set of non-volatile storage elements during a first period using an increasing program signal with a first initial value and subsequently programs the set of non-volatile storage elements during a second period using an increasing program signal with a second initial value, where the second period is subsequent to the first period and the second initial value is different than the first initial value.

公开(公告)号：US20080137411A1

公开(公告)日：2008-06-12

申请号：US12021761

申请日：2008-01-29

申请人： Yupin Fong ,  Jun Wan ,  Jeffrey Lutze

发明人： Yupin Fong ,  Jun Wan ,  Jeffrey Lutze

IPC分类号： G11C16/26

CPC分类号： G11C16/3418 ,  G11C16/3427

摘要： A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.

公开(公告)号：US20080130368A1

公开(公告)日：2008-06-05

申请号：US12018275

申请日：2008-01-23

申请人： Jeffrey Lutze

发明人： Jeffrey Lutze

IPC分类号： G11C16/06

CPC分类号： G11C16/12 ,  G11C16/0483

摘要： A system is disclosed for programming non-volatile storage that improves performance by setting the starting programming voltage to a first level for fresh parts and adjusting the starting programming voltage as the memory is cycled. For example, the system programs a set of non-volatile storage elements during a first period using an increasing program signal with a first initial value and subsequently programs the set of non-volatile storage elements during a second period using an increasing program signal with a second initial value, where the second period is subsequent to the first period and the second initial value is different than the first initial value.

摘要翻译： 公开了一种用于编程非易失性存储器的系统，其通过将起始编程电压设置为新鲜部件的第一电平并在存储器循环时调整起始编程电压来提高性能。 例如，该系统使用具有第一初始值的增加的程序信号在第一时段期间对一组非易失性存储元件进行编程，并且随后使用增加的程序信号在第二周期期间对该组非易失性存储元件进行编程， 第二初始值，其中第二周期在第一周期之后且第二初始值不同于第一初始值。

公开(公告)号：US07265423B2

公开(公告)日：2007-09-04

申请号：US11435456

申请日：2006-05-16

申请人： Nima Mokhlesi ,  Jeffrey Lutze

发明人： Nima Mokhlesi ,  Jeffrey Lutze

IPC分类号： H01L29/76

CPC分类号： H01L27/11 ,  H01L21/28273 ,  H01L21/823437 ,  H01L27/1104 ,  H01L27/115 ,  Y10S257/903

摘要： Various techniques are described which utilize multiple poly-silicon layers in the design and fabrication of various logic elements that are used in semiconductor devices. According to a specific implementation of the present invention, logic gate cell sizes and memory array cell sizes may be reduced by fabricating various transistor gates using multiple poly-silicon layers. The techniques of the present invention of using multiple layers of poly-silicon to form transistor gates of logic elements provides extra degrees of freedom in fine tuning transistor parameters such as, for example, oxide thickness, threshold voltage, maximum allowed gate voltage, etc.

摘要翻译： 描述了在半导体器件中使用的各种逻辑元件的设计和制造中利用多个多晶硅层的各种技术。 根据本发明的具体实现，可以通过使用多个多晶硅层制造各种晶体管栅极来减小逻辑门单元尺寸和存储器阵列单元尺寸。 使用多层多晶硅形成逻辑元件的晶体管栅极的本发明的技术在微调晶体管参数例如氧化物厚度，阈值电压，最大允许栅极电压等中提供了额外的自由度。

公开(公告)号：US07254071B2

公开(公告)日：2007-08-07

申请号：US11332567

申请日：2006-01-12

申请人： Loc Tu ,  Jeffrey Lutze ,  Jun Wan ,  Jian Chen

发明人： Loc Tu ,  Jeffrey Lutze ,  Jun Wan ,  Jian Chen

IPC分类号： G11C29/00

CPC分类号： G11C16/0483 ,  G11C7/16 ,  G11C11/5628 ,  G11C16/04 ,  G11C16/12 ,  G11C16/3454 ,  G11C16/3459 ,  G11C27/005 ,  G11C29/028 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50004 ,  G11C2029/5004 ,  G11C2211/5621 ,  G11C2211/5634

摘要： A flash memory device of the multi-level cell (MLC) type, in which control gate voltages in read and programming operations and a bandgap reference voltage source are trimmable from external terminals, is disclosed. In a special test mode, control gate voltages can be applied to a selected programmed memory cell so that the threshold voltage of the cell can be sensed. A digital-to-analog converter (DAC) use for programming and a second read/verify DAC apply varying analog voltages and are sequentially used to verify the programming of an associated set of memory cells in this special test mode, with the DAC input values that provide the closest result selected for use in normal operation. These DAC's are dependent on the value of a reference source that my also be trimmed.

摘要翻译： 公开了一种多电平单元（MLC）类型的闪速存储器件，其中读取和编程操作中的控制栅极电压和带隙基准电压源可从外部端子进行调节。 在特殊测试模式中，可以将控制栅极电压施加到所选择的编程存储单元，从而可以感测单元的阈值电压。 用于编程的数/模转换器（DAC）和第二读/验用DAC应用变化的模拟电压，并且在该特殊测试模式下依次用于验证相关联的存储器单元的编程，DAC输入值 它提供了选择用于正常操作的最接近的结果。 这些DAC取决于我也被修剪的参考源的值。

公开(公告)号：US20070133295A1

公开(公告)日：2007-06-14

申请号：US11295776

申请日：2005-12-06

申请人： Yupin Fong ,  Jun Wan ,  Jeffrey Lutze

发明人： Yupin Fong ,  Jun Wan ,  Jeffrey Lutze

IPC分类号： G11C16/06

CPC分类号： G11C16/3418 ,  G11C16/3427

摘要： A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.

摘要翻译： 公开了一种用于减少或去除非易失性存储设备中的读取干扰形式的系统。 一个实施例旨在通过消除或最小化存储器元件的通道的升高来防止读取干扰。 例如，一个实施方式在读取过程期间防止或减少NAND串通道的源极侧的升压。 因为NAND串通道的源极侧不被提升，所以读取干扰的至少一种形式被最小化或不发生。

公开(公告)号：US20070086251A1

公开(公告)日：2007-04-19

申请号：US11251458

申请日：2005-10-14

申请人： Jeffrey Lutze ,  Yan Li ,  Siu Chan

发明人： Jeffrey Lutze ,  Yan Li ,  Siu Chan

IPC分类号： G11C7/00

CPC分类号： G11C7/02 ,  G11C7/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621

摘要： The effects of bit line-to-bit line coupling in a non-volatile memory are addressed. An inhibit voltage is applied on a bit line of a storage element to be programmed to inhibit programming during a portion of a program voltage. The inhibit voltage is subsequently removed during the program voltage to allow programming to occur. Due to the proximity of bit lines, the change in the bit line voltage is coupled to a neighboring unselected bit line, reducing the neighboring bit line voltage to a level which might be sufficient to open a select gate and discharge a boost voltage. To prevent this, the select gate voltage is temporarily adjusted during the change in the bit line voltage to ensure that the biasing of the select gate on the unselected bit line is not sufficient to open the select gate.

摘要翻译： 解决位线对位线耦合在非易失性存储器中的影响。 在编程的存储元件的位线上施加禁止电压，以在编程电压的一部分期间禁止编程。 随后在编程电压期间去除抑制电压以允许编程发生。 由于位线的接近，位线电压的变化被耦合到相邻的未选位线，将相邻的位线电压减小到可能足以打开选择栅极并放电升压电压的电平。 为了防止这种情况，在位线电压变化期间临时调整选择栅极电压，以确保未选定位线上的选择栅极的偏置不足以打开选择栅极。