公开(公告)号：US20090268516A1

公开(公告)日：2009-10-29

申请号：US12111729

申请日：2008-04-29

申请人： Mark Murin ,  Menahem Lasser

发明人： Mark Murin ,  Menahem Lasser

IPC分类号： G11C16/06 ,  G11C16/34

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5621

摘要： A method in which non-volatile memory device is accessed using voltages which are customized to the device, and/or to portions of the device, such as blocks or word lines of non-volatile storage elements. The accessing can include programming, verifying or reading. By customizing the voltages, performance can be optimized, including addressing changes in threshold voltage which are caused by program disturb. In one approach, different sets of storage elements in a memory device are programmed with random test data. A threshold voltage distribution is determined for the different sets of storage elements. A set of voltages is determined based on the threshold voltage distribution, and stored in a non-volatile storage location for subsequent use in accessing the different sets of storage elements. The set of voltages may be determined at the time of manufacture for subsequent use in accessing data by the end user.

摘要翻译： 使用针对设备定制的电压和/或设备的诸如非易失性存储元件的块或字线的部分来访问非易失性存储器件的方法。 访问可以包括编程，验证或阅读。 通过定制电压，可以优化性能，包括寻址由程序干扰引起的阈值电压变化。 在一种方法中，存储器件中的不同存储元件组被编程为随机测试数据。 确定不同组的存储元件的阈值电压分布。 一组电压基于阈值电压分布来确定，并存储在非易失性存储位置中，用于随后用于访问不同组的存储元件。 可以在制造时确定该组电压以供随后在最终用户访问数据中使用。

公开(公告)号：US20090168516A1

公开(公告)日：2009-07-02

申请号：US12400662

申请日：2009-03-09

申请人： Mark Murin ,  Mark Shlick

发明人： Mark Murin ,  Mark Shlick

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5642

摘要： Information stored as physical states of cells of a memory is read by setting each of one or more references to a respective member of a first set of values and reading the physical states of the cells according to the first set. Then, at least some of the references are set to respective members of a second set of values, and the physical states of the cells are read according to the second set. At least one member of the second set is different from any member of the first set, so that the two readings together read the physical states of the cells with higher resolution than the first reading alone.

摘要翻译： 通过将一个或多个引用中的每一个设置为第一组值的相应成员并且根据第一组读取单元的物理状态来读取存储为存储器的单元的物理状态的信息。 然后，将至少一些参考设置为第二组值的相应成员，并且根据第二组读取单元的物理状态。 第二组的至少一个成员不同于第一组的任何成员，使得两个读数一起读取比单独的第一读数更高的分辨率的单元的物理状态。

公开(公告)号：US20090113120A1

公开(公告)日：2009-04-30

申请号：US12346676

申请日：2008-12-30

申请人： Mark Murin

发明人： Mark Murin

IPC分类号： G06F12/00

CPC分类号： G11C11/5628

摘要： To store N bits of M≧2 logical pages, the bits are interleaved and the interleaved bits are programmed to [N/M] memory cells, M bits per cell. Preferably, the interleaving puts the same number of bits from each logical page into each bit-page of the [N/M] cells. When the bits are read from the cells, the bits are de-interleaved. The interleaving may be deterministic or random, and may be effected by software or by dedicated hardware.

摘要翻译： 要存储M> = 2个逻辑页的N位，这些位是交错的，并且交织位被编程为[N / M]个存储单元，每个单元M位。 优选地，交织将来自每个逻辑页的相同数量的比特放入[N / M]个小区的每个比特页。 当从单元读取这些位时，这些位被解交织。 交织可以是确定性的或随机的，并且可以由软件或专用硬件实现。

公开(公告)号：US20070106834A1

公开(公告)日：2007-05-10

申请号：US11399343

申请日：2006-04-07

申请人： Mark Murin ,  Mark Shlick

发明人： Mark Murin ,  Mark Shlick

IPC分类号： G06F12/00

CPC分类号： G11C16/26 ,  G06F12/0893 ,  G06F2212/2022

摘要： A flash memory device includes an array of memory cells for storing data pages, at least one buffer (e.g. a memory buffer and a cache buffer) for transferring the data pages to and from the array of memory cells and a host, and an output pin. A logic mechanism is operative to select, from among a plurality of conditions related to an operation on the array of memory cells, a condition that drives a signal being output on the output pin. A data page transfer by the host is contingent on the signal being output on the output pin.

摘要翻译： 闪速存储器件包括用于存储数据页的存储器单元阵列，用于将数据页传送到存储单元阵列和主机的至少一个缓冲器（例如，存储器缓冲器和高速缓冲存储器），以及输出引脚 。 逻辑机构可操作以从与存储器单元阵列上的操作相关的多个条件中选择驱动在输出引脚上输出的信号的条件。 主机的数据页传输取决于输出引脚上输出的信号。

公开(公告)号：US20070091677A1

公开(公告)日：2007-04-26

申请号：US11397609

申请日：2006-04-05

申请人： Menahem Lasser ,  Mark Murin

发明人： Menahem Lasser ,  Mark Murin

IPC分类号： G11C16/06

CPC分类号： G06F11/1072 ,  G06F11/1068 ,  G11C11/5642 ,  G11C16/28

摘要： Methods, devices and computer readable code for reading data from one or more flash memory cells, and for recovering from read errors are disclosed. In some embodiments, in the event of an error correction failure by an error detection and correction module, the flash memory cells are re-read at least once using one or more modified reference voltages, for example, until a successful error correction may be carried out. In some embodiments, after successful error correction a subsequent read request is handled without re-writing data (for example, reliable values of the read data) to the flash memory cells in the interim. In some embodiments, reference voltages associated with a reading where errors are corrected may be stored in memory, and retrieved when responding to a subsequent read request. In some embodiments, the modified reference voltages are predetermined reference voltages. Alternatively or additionally, these modified reference voltages may be determined as needed, for example, using randomly generated values or in accordance with information provided by the error detection and correction module. Methods, devices and computer readable code for reading data for situations where there is no error correction failure are also provided.

摘要翻译： 公开了用于从一个或多个闪存单元读取数据以及从读取错误中恢复的方法，设备和计算机可读代码。 在一些实施例中，在通过错误检测和校正模块进行纠错故障的情况下，例如，可以使用一个或多个修改的参考电压重新读取闪存单元至少一次，直到可以承载成功的纠错 出来 在一些实施例中，在成功的纠错之后，处理随后的读取请求，而不会在此期间将数据（例如，读取数据的可靠值）重新写入闪速存储器单元。 在一些实施例中，与校正错误相关联的读数的参考电压可以存储在存储器中，并在响应随后的读取请求时被检索。 在一些实施例中，修改的参考电压是预定的参考电压。 或者或另外，这些修改的参考电压可以根据需要例如使用随机生成的值或根据由错误检测和校正模块提供的信息来确定。 还提供了用于在没有错误校正失败的情况下读取数据的方法，设备和计算机可读代码。

公开(公告)号：US20070089034A1

公开(公告)日：2007-04-19

申请号：US11329075

申请日：2006-01-11

申请人： Simon Litsyn ,  Idan Alrod ,  Eran Sharon ,  Mark Murin ,  Menahem Lasser

发明人： Simon Litsyn ,  Idan Alrod ,  Eran Sharon ,  Mark Murin ,  Menahem Lasser

IPC分类号： G11C29/00

CPC分类号： G06F11/1072

摘要： A plurality of logical pages is stored in a MBC flash memory along with corresponding ECC bits, with at least one of the MBC cells storing bits from more than one logical page, and with at least one of the ECC bits applying to two or more of the logical pages. When the pages are read from the memory, the data bits as read are corrected using the ECC bits as read. Alternatively, a joint, systematic or non-systematic ECC codeword is computed for two or more of the logical pages and is stored instead of those logical pages. When the joint codeword is read, the logical bits are recovered from the codeword as read. The scope of the invention also includes corresponding memory devices, the controllers of such memory devices, and also computer-readable storage media bearing computer-readable code for implementing the methods.

摘要翻译： 多个逻辑页面与对应的ECC位一起存储在MBC闪速存储器中，其中至少一个MBC单元存储来自多于一个的逻辑页面的位，以及至少一个ECC位应用于两个或多个 逻辑页面。 当从存储器中读取页面时，读取的数据位使用读取的ECC位进行校正。 或者，针对两个或多个逻辑页面计算联合的，系统的或非系统的ECC码字，并且存储该代码字而不是那些逻辑页面。 当读取联合码字时，从读取的码字中恢复逻辑比特。 本发明的范围还包括对应的存储器件，这种存储器件的控制器，以及用于实现该方法的具有计算机可读代码的计算机可读存储介质。

公开(公告)号：US20060155919A1

公开(公告)日：2006-07-13

申请号：US11090177

申请日：2005-03-28

申请人： Menahem Lasser ,  Mark Murin

发明人： Menahem Lasser ,  Mark Murin

IPC分类号： G06F12/00

CPC分类号： G11C11/5628 ,  G11C11/5621 ,  G11C16/0483 ,  G11C2211/5641

摘要： A method of storing data by providing a flash memory device including a plurality of memory cells; each of the memory cells is capable of storing data bits. First data bits are stored into memory cells used for storing M bits per cell, the memory cells are allocated to a page of the memory. Second data bits are stored into other memory cells, the other memory cells used for storing N bits per cell are allocated to the page and upon storing of the first data bits and upon storing the second data bits, the page uses at the same time at least one of the memory cells with M bits per cell and at least one of the other memory cells with N bits per cell with N less than M.

摘要翻译： 一种通过提供包括多个存储器单元的闪存器件来存储数据的方法; 每个存储单元能够存储数据位。 第一数据位被存储到用于存储每个单元的M位的存储器单元中，存储器单元被分配给存储器的页面。 第二数据位被存储到其他存储器单元中，用于存储每个单元N位的其它存储单元被分配给页面并且在存储第一数据位时，并且在存储第二数据位时，页面同时使用 每个单元具有M个位的至少一个存储器单元以及具有N个小于M的每个单元的N位的其它存储单元中的至少一个。

公开(公告)号：US08650462B2

公开(公告)日：2014-02-11

申请号：US12401634

申请日：2009-03-11

申请人： Simon Litsyn ,  Idan Alrod ,  Eran Sharon ,  Mark Murin ,  Menahem Lasser

发明人： Simon Litsyn ,  Idan Alrod ,  Eran Sharon ,  Mark Murin ,  Menahem Lasser

IPC分类号： G11C29/00 ,  H03M13/00

CPC分类号： H03M13/458 ,  G06F11/1012 ,  G06F11/1024 ,  G06F11/1068 ,  G06F11/1072 ,  G11C11/5642 ,  G11C2029/0409 ,  H03M13/45

摘要： Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.

摘要翻译： 根据系统或非系统ECC存储在多比特单元存储器的单元中的数据根据​​估计的概率被读取和校正（系统ECC）或恢复（非系统ECC） 更多的读取位是错误的。 在本发明的一种方法中，估计是先验的。 在本发明的另一种方法中，估计仅基于包括读位的重要性或位页的读位的方面。 在本发明的第三种方法中，估计仅基于读位的值。 并不是所有的估计是相等的。

公开(公告)号：US08443260B2

公开(公告)日：2013-05-14

申请号：US12005368

申请日：2007-12-27

申请人： Mark Shlick ,  Mark Murin ,  Menahem Lasser

发明人： Mark Shlick ,  Mark Murin ,  Menahem Lasser

IPC分类号： G11C29/42 ,  G11C29/54

CPC分类号： G06F11/1064

摘要： A method of storage and retrieval of data in a flash memory system, the flash memory system comprising a cache storage area of relatively high reliability, and a main storage area of relatively low reliability, the method comprising adding to data a level of error correction redundancy higher by a predetermined margin than that required for the cache storage area, writing the data to the cache storage area, and from the cache storage area copying the data directly to the main storage area, the predetermined margin being such as to allow subsequent error correction to compensate for errors accumulated from the cache storage area and the main storage area. In this way the memory die copy back operation can be used for copying the data from the cache to the main memory and two out of four transfers over the data bus to the flash controller are avoided.

公开(公告)号：US08332574B2

公开(公告)日：2012-12-11

申请号：US12102063

申请日：2008-04-14

申请人： Menahem Lasser ,  Mark Murin

发明人： Menahem Lasser ,  Mark Murin

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7207

摘要： User data are stored in a memory that includes one or more blocks of pages by, for one of the blocks, and optionally for all of the blocks, whenever writing any of the user data to that block, writing the block according to a predefined plan for specifying, with respect to each page of that block, a portion of the user data that is to be written to that page. Alternatively or additionally, each page that stores user data has associated therewith a metadatum related to the age of the user data stored therein; and, for one of the blocks, at any time that two or more of the pages of that block store user data, a common value of the metadatum is associated with all such pages.

摘要翻译： 每当将任何用户数据写入该块时，将用户数据存储在包括一个或多个块的块的存储器中，并且可选地针对所有块，并根据预定义的计划写入块 用于针对该块的每个页面指定要写入该页面的用户数据的一部分。 或者或另外，存储用户数据的每个页面与其相关联地存储与其中存储的用户数据的年龄有关的元数据; 并且对于其中一个块，在该块的两个或多个页面存储用户数据的任何时间，元数据的公共值与所有这些页面相关联。