公开(公告)号：US08261157B2

公开(公告)日：2012-09-04

申请号：US12264959

申请日：2008-11-05

申请人： Simon Litsyn ,  Idan Alrod ,  Eran Sharon ,  Mark Murin ,  Menahem Lasser

发明人： Simon Litsyn ,  Idan Alrod ,  Eran Sharon ,  Mark Murin ,  Menahem Lasser

IPC分类号： H03M13/00

CPC分类号： G06F11/1072

摘要： A plurality of logical pages is stored in a MBC flash memory along with corresponding ECC bits, with at least one of the MBC cells storing bits from more than one logical page, and with at least one of the ECC bits applying to two or more of the logical pages. When the pages are read from the memory, the data bits as read are corrected using the ECC bits as read. Alternatively, a joint, systematic or non-systematic ECC codeword is computed for two or more of the logical pages and is stored instead of those logical pages. When the joint codeword is read, the logical bits are recovered from the codeword as read. The scope of the invention also includes corresponding memory devices, the controllers of such memory devices, and also computer-readable storage media bearing computer-readable code for implementing the methods.

摘要翻译： 多个逻辑页面与对应的ECC位一起存储在MBC闪速存储器中，其中至少一个MBC单元存储来自多于一个的逻辑页面的位，以及至少一个ECC位应用于两个或多个 逻辑页面。 当从存储器中读取页面时，读取的数据位使用读取的ECC位进行校正。 或者，针对两个或多个逻辑页面计算联合的，系统的或非系统的ECC码字，并且存储该代码字而不是那些逻辑页面。 当读取联合码字时，从读取的码字中恢复逻辑比特。 本发明的范围还包括对应的存储器件，这种存储器件的控制器，以及用于实现该方法的具有计算机可读代码的计算机可读存储介质。

公开(公告)号：US08009472B2

公开(公告)日：2011-08-30

申请号：US12890267

申请日：2010-09-24

申请人： Mark Murin ,  Menahem Lasser

发明人： Mark Murin ,  Menahem Lasser

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5621

摘要： A method in which non-volatile memory device is accessed using voltages which are customized to the device, and/or to portions of the device, such as blocks or word lines of non-volatile storage elements. The accessing can include programming, verifying or reading. By customizing the voltages, performance can be optimized, including addressing changes in threshold voltage which are caused by program disturb. In one approach, different sets of storage elements in a memory device are programmed with random test data. A threshold voltage distribution is determined for the different sets of storage elements. A set of voltages is determined based on the threshold voltage distribution, and stored in a non-volatile storage location for subsequent use in accessing the different sets of storage elements. The set of voltages may be determined at the time of manufacture for subsequent use in accessing data by the end user.

摘要翻译： 使用针对设备定制的电压和/或设备的部分（诸如非易失性存储元件的块或字线）访问非易失性存储器件的方法。 访问可以包括编程，验证或阅读。 通过定制电压，可以优化性能，包括寻址由程序干扰引起的阈值电压变化。 在一种方法中，存储器件中的不同存储元件组被编程为随机测试数据。 确定不同组的存储元件的阈值电压分布。 一组电压基于阈值电压分布来确定，并且存储在非易失性存储位置中，用于随后用于访问不同组的存储元件。 可以在制造时确定该组电压以供随后在最终用户访问数据中使用。

公开(公告)号：US07992071B2

公开(公告)日：2011-08-02

申请号：US12814917

申请日：2010-06-14

申请人： Mark Murin

发明人： Mark Murin

IPC分类号： G11C29/00

CPC分类号： G06F11/1068

摘要： A method in a data storage device for storing a plurality of data bits into a non-volatile memory includes transforming a plurality of data bits to be stored in a non-volatile memory device to generate a plurality of transformed data bits. The method further includes generating a parity bit corresponding to the plurality of transformed data bits, transforming the parity bit, and storing the plurality of data bits and the transformed parity bit in the non-volatile memory device. Each of the plurality of data bits and the parity bit form an all-one codeword.

摘要翻译： 用于将多个数据位存储到非易失性存储器中的数据存储设备中的方法包括：变换要存储在非易失性存储器件中的多个数据位，以产生多个经变换的数据位。 该方法还包括产生对应于多个变换数据位的奇偶校验位，变换奇偶校验位，并将多个数据位和变换后的奇偶校验位存储在非易失性存储器件中。 多个数据位和奇偶校验位中的每一个形成全1码字。

公开(公告)号：US07954037B2

公开(公告)日：2011-05-31

申请号：US11397609

申请日：2006-04-05

申请人： Menahem Lasser ,  Mark Murin

发明人： Menahem Lasser ,  Mark Murin

IPC分类号： G11C29/00

CPC分类号： G06F11/1072 ,  G06F11/1068 ,  G11C11/5642 ,  G11C16/28

摘要： Methods, devices and computer readable code for reading data from one or more flash memory cells, and for recovering from read errors are disclosed. In some embodiments, in the event of an error correction failure by an error detection and correction module, the flash memory cells are re-read at least once using one or more modified reference voltages, for example, until a successful error correction may be carried out. In some embodiments, after successful error correction a subsequent read request is handled without re-writing data (for example, reliable values of the read data) to the flash memory cells in the interim. In some embodiments, reference voltages associated with a reading where errors are corrected may be stored in memory, and retrieved when responding to a subsequent read request. In some embodiments, the modified reference voltages are predetermined reference voltages. Alternatively or additionally, these modified reference voltages may be determined as needed, for example, using randomly generated values or in accordance with information provided by the error detection and correction module. Methods, devices and computer readable code for reading data for situations where there is no error correction failure are also provided.

摘要翻译： 公开了用于从一个或多个闪存单元读取数据以及从读取错误中恢复的方法，设备和计算机可读代码。 在一些实施例中，在通过错误检测和校正模块进行纠错故障的情况下，例如，可以使用一个或多个修改的参考电压重新读取闪存单元至少一次，直到可以承载成功的纠错 出来 在一些实施例中，在成功的纠错之后，处理随后的读取请求，而不会在此期间将数据（例如，读取数据的可靠值）重新写入闪速存储器单元。 在一些实施例中，与校正错误相关联的读数的参考电压可以存储在存储器中，并在响应随后的读取请求时被检索。 在一些实施例中，修改的参考电压是预定的参考电压。 或者或另外，这些修改的参考电压可以根据需要例如使用随机生成的值或根据由错误检测和校正模块提供的信息来确定。 还提供了用于在没有错误校正失败的情况下读取数据的方法，设备和计算机可读代码。

公开(公告)号：US20100274962A1

公开(公告)日：2010-10-28

申请号：US12430089

申请日：2009-04-26

申请人： Amir MOSEK ,  Menahem LASSER ,  Mark MURIN

发明人： Amir MOSEK ,  Menahem LASSER ,  Mark MURIN

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0804 ,  G06F12/0868 ,  G06F12/0888 ,  G06F2212/214

摘要： The present disclosure relates to methods, devices and computer-readable medium for implementing a caching policy and/or a cache flushing policy in a peripheral non-volatile storage device operatively coupled to a host device. In some embodiments, data is stored to a cache area of a non-volatile memory within the peripheral non-volatile storage device in accordance with a historical rate at which other data was received by the peripheral storage device from the host device and/or a historical average time interval between successive host write requests received and/or an assessed rate at which data is required to be written to the non-volatile memory and/or a detecting by the peripheral non-volatile memory device that the host has read the storage ready/busy flag. In some embodiments, data is copied from a cache storage area of the non-volatile memory to a main storage area in accordance with the historical rate and/or the historical average time interval.

摘要翻译： 本公开涉及用于在可操作地耦合到主机设备的外围非易失性存储设备中实现高速缓存策略和/或缓存刷新策略的方法，设备和计算机可读介质。 在一些实施例中，根据外围存储设备从主机设备接收其他数据的历史速率和/或一个或多个存储器，数据被存储到外围非易失性存储设备内的非易失性存储器的高速缓存区域 接收的连续主机写入请求和/或需要将数据写入非易失性存储器的评估速率和/或由外围非易失性存储器设备检测到主机已读取存储器的历史平均时间间隔 准备/忙碌标志 在一些实施例中，根据历史速率和/或历史平均时间间隔将数据从非易失性存储器的高速缓存存储区域复制到主存储区域。

公开(公告)号：US20100274955A1

公开(公告)日：2010-10-28

申请号：US12830001

申请日：2010-07-02

申请人： Menahem Lasser ,  Mark Murin ,  Arik Eyal

发明人： Menahem Lasser ,  Mark Murin ,  Arik Eyal

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G11C11/5621 ,  G06F12/0246 ,  G06F12/0866 ,  G06F2212/2022 ,  G06F2212/7211 ,  G11C16/349 ,  G11C16/3495 ,  G11C2211/5641

摘要： A flash memory storage system includes a memory array containing a plurality of memory cells and a controller for controlling the flash memory array. The controller dedicates a first group of memory cells to operate with a first number of bits per cell and a second, separate group of memory cells to operate with a second number of bits per cell. A mechanism is provided to apply wear leveling techniques separately to the two groups of cells to evenly wear out the memory cells.

摘要翻译： 闪速存储器存储系统包括包含多个存储器单元的存储器阵列和用于控制闪速存储器阵列的控制器。 控制器专用于第一组存储器单元以每个单元的第一个位数和第二个单独的存储器单元组以每个单元的第二个位数来操作。 提供了一种机制来将磨损均衡技术分别应用于两组细胞以均匀地磨损存储单元。

公开(公告)号：US20100199135A1

公开(公告)日：2010-08-05

申请号：US12755519

申请日：2010-04-07

申请人： MARK MURIN ,  MENAHEM LASSER ,  AVRAHAM MEIR

发明人： MARK MURIN ,  MENAHEM LASSER ,  AVRAHAM MEIR

IPC分类号： G06F11/273 ,  G06F12/02

CPC分类号： G11C29/48 ,  G01R31/318513 ,  G11C29/1201 ,  G11C2029/0401 ,  G11C2029/1208

摘要： A flash memory device includes a flash memory residing on at least one flash memory die. The flash memory device also includes a flash controller residing on a flash controller die that is separate from the at least one flash memory die. The flash memory and the flash controller reside within, reside on, or are attached to a common housing. The flash controller is configured to execute at least one test program to test at least one flash memory die.

摘要翻译： 闪存设备包括驻留在至少一个闪存存储器模块上的闪存。 闪存设备还包括驻留在闪存控制器管芯上的与至少一个闪存管芯分离的闪存控制器。 闪存和闪存控制器驻留在，驻留在或连接到公共外壳。 闪存控制器被配置为执行至少一个测试程序来测试至少一个闪存芯片。

公开(公告)号：US20100005370A1

公开(公告)日：2010-01-07

申请号：US12401629

申请日：2009-03-11

申请人： Simon LITSYN ,  Idan Alrod ,  Eran Sharon ,  Mark Murin ,  Menahem Lasser

发明人： Simon LITSYN ,  Idan Alrod ,  Eran Sharon ,  Mark Murin ,  Menahem Lasser

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/458 ,  G06F11/1012 ,  G06F11/1024 ,  G06F11/1068 ,  G06F11/1072 ,  G11C11/5642 ,  G11C2029/0409 ,  H03M13/45

摘要： Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.

公开(公告)号：US07613045B2

公开(公告)日：2009-11-03

申请号：US11945120

申请日：2007-11-26

申请人： Mark Murin ,  Mark Shlick ,  Menahem Lasser ,  Cuong Trinh

发明人： Mark Murin ,  Mark Shlick ,  Menahem Lasser ,  Cuong Trinh

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C11/5642 ,  G11C16/26 ,  G11C2211/5631 ,  G11C2211/5634

摘要： A memory device generates one or more read reference voltages rather than being explicitly supplied with each read reference voltage from an external host controller. The technique involves providing a command to the memory device that causes a reading of a set of storage elements by the memory device using a reference voltage which is different than a reference voltage used in a previous reading, where the new read reference value is not explicitly set outside the memory device. In one implementation, the memory device is provided with an initial reference voltage and a step size for generating additional reference voltages. The technique can be used, e.g., in determining a threshold voltage distribution of a set of storage elements. In this case, a voltage sweep can be applied to a word line associated with the set of storage elements, and data obtained based on the number of conductive storage elements.

摘要翻译： 存储器件产生一个或多个读取参考电压，而不是明确地提供来自外部主机控制器的每个读取参考电压。 该技术涉及向存储器件提供命令，其使得存储器件使用不同于先前读取中使用的参考电压的参考电压来读取一组存储元件，其中新的读取参考值不是明确的 设置在存储设备外面。 在一个实现中，存储器件被提供有初始参考电压和用于产生附加参考电压的步长。 该技术可以用于例如确定一组存储元件的阈值电压分布。 在这种情况下，可以对与该组存储元件相关联的字线施加电压扫描，并且可以基于导电存储元件的数量获得的数据。

公开(公告)号：US07526715B2

公开(公告)日：2009-04-28

申请号：US11339571

申请日：2006-01-26

申请人： Simon Litsyn ,  Idan Alrod ,  Eran Sharon ,  Mark Murin ,  Menahem Lasser

发明人： Simon Litsyn ,  Idan Alrod ,  Eran Sharon ,  Mark Murin ,  Menahem Lasser

IPC分类号： H03M13/00

CPC分类号： H03M13/458 ,  G06F11/1012 ,  G06F11/1024 ,  G06F11/1068 ,  G06F11/1072 ,  G11C11/5642 ,  G11C2029/0409 ,  H03M13/45

摘要： Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.

摘要翻译： 根据系统或非系统ECC存储在多比特单元存储器的单元中的数据根据​​估计的概率被读取和校正（系统ECC）或恢复（非系统ECC） 更多的读取位是错误的。 在本发明的一种方法中，估计是先验的。 在本发明的另一种方法中，估计仅基于包括读位的重要性或位页的读位的方面。 在本发明的第三种方法中，估计仅基于读位的值。 并不是所有的估计是相等的。