公开(公告)号：US20140021981A1

公开(公告)日：2014-01-23

申请号：US13555014

申请日：2012-07-20

Applicant: Michael D. Hutton

Inventor： Michael D. Hutton

IPC: H03K19/173

CPC classification number: G06F17/5054 ,  H03K19/17744

Abstract: Integrated circuits such as programmable integrated circuits may include programmable logic regions that can be configured to perform custom functions. Interconnects may be used to route signals throughout the integrated circuit. The programmable logic regions may have input selection circuitry for selecting and providing input signals from the interconnects to the programmable logic regions. The programmable logic regions may include look-up table circuitry for processing the input signals and registers for storing output signals from the look-up table circuitry. The programmable logic regions may include output selection circuitry for selecting which output signals are provided to output circuitry of the programmable logic regions. The programmable logic regions may include bypass paths that provide direct access to the registers from the interconnects by bypassing the input and output selection circuitry. Computer-aided design tools may be used to identify registers in a design that should be used for register pipelining.

Abstract translation: 诸如可编程集成电路的集成电路可以包括可被配置为执行定制功能的可编程逻辑区域。 互连可用于在整个集成电路中路由信号。 可编程逻辑区域可以具有输入选择电路，用于选择并提供从互连到可编程逻辑区域的输入信号。 可编程逻辑区域可以包括用于处理输入信号的查找表电路和用于存储来自查找表电路的输出信号的寄存器。 可编程逻辑区域可以包括用于选择向可编程逻辑区域的输出电路提供哪些输出信号的输出选择电路。 可编程逻辑区域可以包括通过旁路输入和输出选择电路来提供从互连对寄存器的直接访问的旁路路径。 计算机辅助设计工具可用于识别应用于注册流水线的设计中的寄存器。

公开(公告)号：US08542032B1

公开(公告)日：2013-09-24

申请号：US13345436

申请日：2012-01-06

Applicant: Michael D. Hutton ,  Irfan Rahim

Inventor： Michael D. Hutton ,  Irfan Rahim

IPC: H03K19/173

CPC classification number: G06F17/5054 ,  G06F17/5031 ,  G06F17/5059 ,  G06F2217/06 ,  G06F2217/08 ,  G06F2217/82 ,  G06F2217/84 ,  H03K19/1737 ,  H03K19/17736 ,  H03K19/1776

Abstract: Integrated circuits such as programmable integrated circuits may include programmable logic regions that can be configured to perform custom user functions. The programmable logic regions may produce output signals. The integrated circuit may include interconnects that route selected output signals throughout the integrated circuit. The integrated circuit may include output selection circuitry having output selection and interconnect selection stages. The output selection circuitry may be configured to select which of the output signals produced by the programmable logic regions are provided to the interconnects for routing. The interconnect selection stage may be formed using multiplexing circuits or tristate drivers. Logic design system computing equipment may be used to generate configuration data that can be used to program the output selection circuitry to reduce crosstalk by routing signals away from critical interconnects or by double-driving critical interconnects.

Abstract translation: 诸如可编程集成电路的集成电路可以包括可被配置为执行定制用户功能的可编程逻辑区域。 可编程逻辑区域可以产生输出信号。 集成电路可以包括在整个集成电路中路由选择的输出信号的互连。 集成电路可以包括具有输出选择和互连选择阶段的输出选择电路。 输出选择电路可以被配置为选择由可编程逻辑区域产生的输出信号中的哪一个被提供给用于路由的互连。 可以使用多路复用电路或三态驱动器来形成互连选择级。 逻辑设计系统计算设备可用于产生可用于对输出选择电路编程的配置数据，以通过将信号路由远离关键互连或通过双重驱动关键互连来减少串扰。

公开(公告)号：US08381142B1

公开(公告)日：2013-02-19

申请号：US11973470

申请日：2007-10-09

Applicant: Michael D. Hutton

Inventor： Michael D. Hutton

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F2217/84

Abstract: A method for designing a system on a target device is described. In one embodiment of the method, a plurality of registers is replaced with at least one register and a timing exception. In one embodiment, the registers in the plurality of registers are in series or substantially in series. In one embodiment, the timing exception is a multi-cycle exception. In one embodiment, the method also includes identifying a critical combinational logic path that is followed or preceded by the plurality of registers. Further, in one aspect, the timing exception is removed and registers are inserted into the critical combinational logic path to account for the removed timing exception. In one embodiment, a network flow algorithm is performed to determine the locations for inserting registers.

Abstract translation: 描述了在目标设备上设计系统的方法。 在该方法的一个实施例中，多个寄存器被替换为至少一个寄存器和定时异常。 在一个实施例中，多个寄存器中的寄存器串联或基本上串联。 在一个实施例中，定时异常是多循环异常。 在一个实施例中，该方法还包括识别跟随或之前的多个寄存器的关键组合逻辑路径。 此外，在一个方面，消除了定时异常，并且将寄存器插入到关键组合逻辑路径中，以解决去除的定时异常。 在一个实施例中，执行网络流程算法以确定用于插入寄存器的位置。

公开(公告)号：US08166427B1

公开(公告)日：2012-04-24

申请号：US12044926

申请日：2008-03-07

Applicant: Swatiben Ruturaj Pathak ,  Babette Van Antwerpen ,  Michael D. Hutton ,  Andrew Leaver

Inventor： Swatiben Ruturaj Pathak ,  Babette Van Antwerpen ,  Michael D. Hutton ,  Andrew Leaver

IPC: G06F17/50

CPC classification number: G06F17/5054

Abstract: Circuits, methods, software, and apparatus that track the removal of, reasons for, and consequence of the removal of registers or other circuitry during the synthesis of electronic circuits. An exemplary embodiment of the present invention tracks the removal of registers and determines why the registers were removed. This information is then provided in an efficient manner for design debugging purposes.

Abstract translation: 跟踪在电子电路合成过程中去除寄存器或其他电路的原因和结果的电路，方法，软件和设备。 本发明的示例性实施例跟踪寄存器的移除并确定为什么寄存器被去除。 然后以有效的方式提供该信息用于设计调试目的。

公开(公告)号：US08108812B1

公开(公告)日：2012-01-31

申请号：US12749514

申请日：2010-03-30

Applicant: Babette van Antwerpen ,  Michael D. Hutton ,  Gregg Baeckler ,  Richard Yuan

Inventor： Babette van Antwerpen ,  Michael D. Hutton ,  Gregg Baeckler ,  Richard Yuan

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F17/5045

Abstract: An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.

Abstract translation: 电子自动化系统对逻辑设计执行寄存器重新定时，这可能是可编程逻辑集成电路的逻辑设计。 寄存器重新定时是设计中组合逻辑寄存器的移动或重排，以提高最大工作频率或fmax。 在一个实现中，该系统包括机器可读代码，其可以存储在计算机上执行的诸如磁盘的计算机可读介质上。 系统平衡时间，以便折中关键路径和非关键路径之间的延迟。 注册重新定时可能会改变门级设计。

公开(公告)号：US08001499B1

公开(公告)日：2011-08-16

申请号：US12053481

申请日：2008-03-21

Applicant: Greg William Baeckler ,  David W. Mendel ,  Michael D. Hutton

Inventor： Greg William Baeckler ,  David W. Mendel ,  Michael D. Hutton

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5054

Abstract: A pragma is used to pass circuit type information to a Computer Aided design (CAD) tool. The CAD tool then selects an alternate synthesis or timing algorithm based on the circuit type, and a circuit design for use in an electronic device is created. Practical applications include using alternate algorithms specific to different circuit types, such as, Cyclic Redundancy Checks (CRC), bus arbiters, state machine encoders, barrel shifters, preferential cores, and legacy circuits. One embodiment generates informative messages for the designer once the circuit type is known and the analysis is performed. Another embodiment generates pragmas that can be later used by circuit designers in future circuit designs.

Abstract translation: 使用编译指令将电路类型信息传递到计算机辅助设计（CAD）工具。 然后，CAD工具基于电路类型选择替代合成或定时算法，并且创建用于电子设备的电路设计。 实际应用包括使用特定于不同电路类型的替代算法，例如循环冗余校验（CRC），总线仲裁器，状态机编码器，桶形移位器，优先核心和传统电路。 一旦实施了电路类型并且执行了分析，一个实施例为设计者生成信息性消息。 另一个实施例产生可以在将来的电路设计中由电路设计者稍后使用的编译指示。

公开(公告)号：US07827433B1

公开(公告)日：2010-11-02

申请号：US11804157

申请日：2007-05-16

Applicant: Michael D. Hutton

Inventor： Michael D. Hutton

IPC: G06F5/06

CPC classification number: H03M9/00 ,  G06F7/68

Abstract: Serializing circuitry is provided that can multiplex multiple device output signals and that can drive time-multiplexed data signals on the bus wires of a data path of an electronic system. Bus registers placed at the ends of the bus wires can register or buffer the data signals transmitted over the bus wires. The registered signals may be passed on to deserializing circuitry for demultiplexing the data signals to provide parallel device input signals. The bus registers and the serializing/deserializing circuitry can be provided along signal paths that require additional latency.

Abstract translation: 提供了可以复用多个设备输出信号并且可以在电子系统的数据路径的总线上驱动时间复用数据信号的序列化电路。 放置在总线末端的总线寄存器可以对通过总线进行传输的数据信号进行寄存或缓冲。 注册的信号可以被传递到用于解复用数据信号以提供并行设备输入信号的反序列化电路。 总线寄存器和序列化/反序列化电路可以沿着需要额外延迟的信号路径提供。

公开(公告)号：US07689955B1

公开(公告)日：2010-03-30

申请号：US11513450

申请日：2006-08-30

Applicant: Babette van Antwerpen ,  Michael D. Hutton ,  Gregg Baeckler ,  Richard Yuan

Inventor： Babette van Antwerpen ,  Michael D. Hutton ,  Gregg Baeckler ,  Richard Yuan

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F17/5045

Abstract: An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.

Abstract translation: 电子自动化系统对逻辑设计执行寄存器重新定时，这可能是可编程逻辑集成电路的逻辑设计。 寄存器重新定时是设计中组合逻辑寄存器的移动或重排，以提高最大工作频率或fmax。 在一个实现中，该系统包括机器可读代码，其可以存储在计算机上执行的诸如磁盘的计算机可读介质上。 系统平衡时间，以便折中关键路径和非关键路径之间的延迟。 注册重新定时可能会改变门级设计。

公开(公告)号：US20100026340A1

公开(公告)日：2010-02-04

申请号：US12577061

申请日：2009-10-09

Applicant: Michael D. Hutton ,  Andy L. Lee

Inventor： Michael D. Hutton ,  Andy L. Lee

IPC: H03K19/177

CPC classification number: H03K19/17748 ,  H03K19/17784

Abstract: A programmable logic device (PLD) includes a configuration circuit, and first and second freeze-logic circuits. The configuration circuit provides configuration data for configuring programmable resources of the PLD during a configuration mode of the PLD. One of the two freeze-logic circuits provides a freeze logic signal during the configuration mode of the PLD. The other freeze-logic circuit provides a freeze logic signal during a user mode of the PLD.

Abstract translation: 可编程逻辑器件（PLD）包括配置电路以及第一和第二冻结逻辑电路。 配置电路提供用于在PLD的配置模式期间配置PLD的可编程资源的配置数据。 两个冻结逻辑电路之一在PLD的配置模式期间提供冻结逻辑信号。 另一个冻结逻辑电路在PLD的用户模式期间提供冻结逻辑信号。

公开(公告)号：US07368944B1

公开(公告)日：2008-05-06

申请号：US11649748

申请日：2007-01-03

Applicant: Michael D. Hutton ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  David Lewis ,  Tim Vanderhoek

Inventor： Michael D. Hutton ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  David Lewis ,  Tim Vanderhoek

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/17728

Abstract: A programmable logic element grouping for use in multiple instances on a programmable logic device includes more than the traditional number of logic elements sharing secondary signal (e.g., clock, clock enable, clear, etc.) selection circuitry. The logic elements in such a grouping are divided into at least two subgroups. Programmable interconnection circuitry is provided for selectively applying signals from outside the grouping and signals fed back from the logic elements in the grouping to primary inputs of the logic elements in the grouping. The programmable interconnection circuitry limits possible application of at least some of these signals to one or the other of the subgroups, and/or provides for possible application of at least some of these signals to a greater percentage of the primary inputs to one of the subgroups than to the other.

Abstract translation: 在可编程逻辑器件上的多个实例中使用的可编程逻辑元件组合包括多于共享次级信号（例如，时钟，时钟使能，清零等）选择电路的传统数量的逻辑元件。 这种分组中的逻辑元素被划分为至少两个子组。 提供了可编程互连电路，用于选择性地将分组外的信号和分组中的逻辑元件反馈的信号分组中的逻辑元件的主要输入。 可编程互连电路将这些信号中的至少一些信号的可能应用限制到子组中的一个或另一个，并且/或提供这些信号中的至少一些信号到其中一个子组的较大百分比的主要输入的可能应用 比对方。