公开(公告)号：US06462397B2

公开(公告)日：2002-10-08

申请号：US10027583

申请日：2001-10-22

Applicant: Byung Ryul Ryum ,  Tae Hyeon Han ,  Soo Min Lee ,  Deok Ho Cho

Inventor： Byung Ryul Ryum ,  Tae Hyeon Han ,  Soo Min Lee ,  Deok Ho Cho

IPC: H01L27082

CPC classification number: H01L29/66287 ,  H01L29/66242

Abstract: The present invention is related to a bipolar transistor in which the in-situ doped epitaxial Si or SiGe base layer is used instead of using an ion-implanted Si base, in order to achieve higher cutoff frequency. The SiGe base having the narrower energy bandgap than the Si emitter allows to enhance the current gain, the cutoff frequency(fT), and the maximum oscillation frequency (fmax). The narrow bandgap SiGe base also allows to have higher base doping concentration. As a result, the intrinsic base resistance is lowered and the noise figure is thus lowered. Parasitic base resistance is also minimized by using a metallic silicide base ohmic electrode. The present invention is focused on low cost, high repeatability and reliability by simplifying the manufacturing process step.

Abstract translation: 本发明涉及一种双极晶体管，其中使用原位掺杂的外延Si或SiGe基层代替使用离子注入的Si基，以便实现更高的截止频率。 具有比Si发射器更窄的能带隙的SiGe基极允许增强电流增益，截止频率（fT）和最大振荡频率（fmax）。 窄带隙SiGe基极还允许具有较高的基极掺杂浓度。 结果，本征基极电阻降低，噪声系数降低。 通过使用金属硅化物基极欧姆电极也使寄生基极电阻最小化。 通过简化制造工艺步骤，本发明集中在低成本，高重复性和可靠性上。

公开(公告)号：US6140195A

公开(公告)日：2000-10-31

申请号：US213868

申请日：1998-12-17

Applicant: Byung-Ryul Ryum ,  Soo-Min Lee ,  Deok-Ho Cho ,  Tae-Hyeon Han

Inventor： Byung-Ryul Ryum ,  Soo-Min Lee ,  Deok-Ho Cho ,  Tae-Hyeon Han

IPC: H01L21/328 ,  H01L21/331 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/0649 ,  H01L29/0821 ,  H01L29/66265 ,  H01L29/66272

Abstract: The present invention provides a collector device in a bipolar device, having a lateral collector structure on a buried oxide layer. This collector has a high breakdown voltage for high power and operating at a high speed, by isolating a horizontal collector from a substrate by a buried oxide film and horizontally connecting a buried collector to a collector. The buried collector film is formed on the buried insulating film, surrounding the collector film and being horizontally connected to the collector film.

Abstract translation: 本发明提供一种在双极器件中的集电极器件，其在掩埋氧化物层上具有横向收集器结构。 该集电极具有高功率的高击穿电压并以高速工作，通过埋入氧化膜将水平集电器与衬底隔离并将埋入式收集器水平连接到集电器。 埋置的集电体膜形成在埋入绝缘膜上，围绕集电体膜并且与集电体膜水平连接。

公开(公告)号：US06124614A

公开(公告)日：2000-09-26

申请号：US233329

申请日：1999-01-20

Applicant: Byung-Ryul Ryum ,  Soo-Min Lee ,  Deok-Ho Cho ,  Tae-Hyeon Han

Inventor： Byung-Ryul Ryum ,  Soo-Min Lee ,  Deok-Ho Cho ,  Tae-Hyeon Han

IPC: H01L27/06 ,  H01L21/336 ,  H01L29/10 ,  H01L29/417 ,  H01L29/45 ,  H01L27/01 ,  H01L21/249

CPC classification number: H01L29/66477 ,  H01L29/1054 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66651

Abstract: The present invention relates to a metal silicon field effect transistor (MOSFET), and more particularly to a MOSFET, using a Si or SiGe channel to effectively adjust threshold voltage. The transistor according to the present invention can solve the problems, such as the punch-through caused by the short distance between the source region and the drain region, the decrease of the breakdown voltage between the source region and the drain region and the leakage current flowing into the bulk region beneath the channel due to the drain-induced barrier lowering. Furthermore, because the source region and the drain region are isolated from the semiconductor substrate by the lower insulation layer, the removal of the parasite junction capacitor speed up the transistor.

Abstract translation: 本发明涉及金属硅场效应晶体管（MOSFET），更具体地说，涉及一种使用Si或SiGe沟道来有效调节阈值电压的MOSFET。 根据本发明的晶体管可以解决诸如源极区域和漏极区域之间的短距离引起的穿通，源极区域和漏极区域之间的击穿电压的降低以及漏电流的问题 由于漏极引起的屏障降低，流入通道下方的体区域。 此外，由于源极区域和漏极区域通过下部绝缘层与半导体衬底隔离，因此去除寄生电容器电容器加速了晶体管。

公开(公告)号：US5484737A

公开(公告)日：1996-01-16

申请号：US357244

申请日：1994-12-13

Applicant: Byung-Ryul Ryum ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Deok-Ho Cho ,  Seong-Hearn Lee ,  Jin-Young Kang

Inventor： Byung-Ryul Ryum ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Deok-Ho Cho ,  Seong-Hearn Lee ,  Jin-Young Kang

IPC: H01L21/331 ,  H01L29/732 ,  H01L29/737 ,  H01L21/8222

CPC classification number: H01L29/66242 ,  H01L29/732 ,  H01L29/7378 ,  Y10S148/059 ,  Y10S148/067

Abstract: Disclosed is a fabrication of a bipolar transistor with a super self-aligned vertical structure in which emitter, base and collector are vertically self-aligned, the fabrication method comprising the steps of forming a conductive buried collector region in a silicon substrate by using ion-implantation of an impurity and thermal-annealing; sequentially forming several layers; selectively removing the nitride and polysilicon layers to form a pattern; sequentially forming a silicon oxide layer, a third layer and a silicon oxide layer thereon; forming a patterned photoresist layer thereon to define active and inactive regions and removing several layers on the active region to form an opening; forming a side wall on both sides of the opening; forming a collector on a surface portion of the buried collector region up to a lower surface of the polysilicon layer; removing the side wall and the third nitride layer to expose a side surface of the second polysilicon layer; selectively forming a base on an upper surface of the collector including a side surface of the polysilicon layer; forming side wall oxide layer on both sides of the base and the silicon oxide to define an emitter region; forming an emitter on the base; and forming electrodes thereon. In the method, an active region is defined by a photolithography, and thereby a trench isolation acting as factors of lowering in integration and device-performance can be omitted in the method. As a result, fabrication sequence can be simplified and integration can be improved.

Abstract translation: 公开了一种具有超自对准垂直结构的双极晶体管的制造，其中发射极，基极和集电极垂直自对准，所述制造方法包括以下步骤：通过使用离子交换膜在硅衬底中形成导电掩埋集电极区域， 注入杂质和热退火; 依次形成几层; 选择性地去除氮化物和多晶硅层以形成图案; 在其上依次形成氧化硅层，第三层和氧化硅层; 在其上形成图案化的光致抗蚀剂层以限定活性和非活性区域并去除活性区域上的多个层以形成开口; 在开口的两侧形成侧壁; 在所述掩埋集电极区域的表面部分上形成集电体直到所述多晶硅层的下表面; 去除侧壁和第三氮化物层以暴露第二多晶硅层的侧表面; 在所述集电体的上表面上选择性地形成基底，所述基底包括所述多晶硅层的侧表面; 在所述基底和所述氧化硅的两侧上形成侧壁氧化物层以限定发射极区域; 在基底上形成发射体; 并在其上形成电极。 在该方法中，通过光刻法定义有源区，因此可以在该方法中省略作为降低集成度和器件性能的因素的沟槽隔离。 结果，可以简化制造顺序并且可以提高集成。

公开(公告)号：US5444014A

公开(公告)日：1995-08-22

申请号：US357021

申请日：1994-12-16

Applicant: Byung-Ryul Ryum ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Deok-Ho Cho ,  Seong-Hearn Lee ,  Jin-Young Kang

Inventor： Byung-Ryul Ryum ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Deok-Ho Cho ,  Seong-Hearn Lee ,  Jin-Young Kang

IPC: H01L21/331 ,  H01L21/762 ,  H01L21/76

CPC classification number: H01L29/66287 ,  H01L21/76264 ,  H01L21/76294 ,  H01L29/66265 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/76286 ,  Y10S148/012

Abstract: Disclosed is a method of fabricating an SOI substrate, comprising the steps of forming a first insulating layer on a single crystal silicon substrate; patterning the first insulating layer to form an opening; growing a single crystal silicon in the opening to form active and inactive regions; polishing the active region 31 as the first insulating layer as a polishing stopper to form a planarized surface; depositing a second insulating layer on the planarized surface; bonding a bonding substrate to the second insulating layer; and polishing the silicon substrate using the first insulating layer as a stopper up to a surface of the active region. By the method, a stray capacitance occurring between an SOI substrate and a metal wiring portion formed thereon can be significantly reduced owing to a relatively thick insulating layer therebetween, and a parasitic capacitance can be eliminated owing to an insulating layer interposed between a bonding substrate and an active region to be used as a buried collector.

Abstract translation: 公开了一种制造SOI衬底的方法，包括以下步骤：在单晶硅衬底上形成第一绝缘层; 图案化第一绝缘层以形成开口; 在开口中生长单晶硅以形成活性和非活性区域; 将作为第一绝缘层的有源区域31抛光为抛光停止层以形成平坦化表面; 在平坦化表面上沉积第二绝缘层; 将接合基板接合到所述第二绝缘层; 以及使用所述第一绝缘层作为阻挡物直到所述有源区的表面来研磨所述硅衬底。 通过该方法，由于SOI衬底和形成在其上的金属布线部分之间的寄生电容由于其之间的相对较厚的绝缘层而可以显着降低，并且由于绝缘层介于接合衬底和 用作埋藏式收集器的有源区域。