公开(公告)号：US06337494B1

公开(公告)日：2002-01-08

申请号：US09137709

申请日：1998-08-21

Applicant: Byung Ryul Ryum ,  Deok Ho Cho ,  Tae Hyeon Han ,  Soo Min Lee

Inventor： Byung Ryul Ryum ,  Deok Ho Cho ,  Tae Hyeon Han ,  Soo Min Lee

IPC: H01L310328

CPC classification number: H01L29/1602 ,  H01L29/16 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7378

Abstract: Disclosed is a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof without using a trench isolation process and a sophisticated selective epitaxial growth (SEG) processes. According to this invention, the sophisticated isolation and the SEG techniques are derived by using simple and popular processes. The base layer has multi-layer structure being made of a Si, an undoped SiGe, a SiGe doped a p-type impurity in-situ and Si. Also, the selective epitaxial growth is not required. Thus, it can be less prone to a flow of leakage current or an emitter-base-collector short effect.

Abstract translation: 公开了能够使元件小型化的超自对准异质结双极晶体管，简化了其工艺步骤，而不使用沟槽隔离工艺和复杂的选择性外延生长（SEG）工艺。 根据本发明，通过使用简单和流行的方法得到复杂的隔离和SEG技术。 基层具有由Si，未掺杂的SiGe，SiGe原位掺杂p型杂质的Si和Si构成的多层结构。 此外，不需要选择性外延生长。 因此，可能不太容易发生漏电流或发射极 - 基极 - 集电极短路效应。

公开(公告)号：US5798277A

公开(公告)日：1998-08-25

申请号：US729841

申请日：1996-10-15

Applicant: Byung-Ryul Ryum ,  Tae-Hyeon Han ,  Deok-Ho Cho ,  Soo-Min Lee ,  Kwang-Eui Pyun

Inventor： Byung-Ryul Ryum ,  Tae-Hyeon Han ,  Deok-Ho Cho ,  Soo-Min Lee ,  Kwang-Eui Pyun

IPC: H01L29/70 ,  H01L21/331 ,  H01L29/08 ,  H01L29/737 ,  H01L21/265

CPC classification number: H01L29/66242 ,  H01L29/0821 ,  H01L29/7371 ,  Y10S148/05 ,  Y10S148/072

Abstract: An improved method for fabricating a heterojunction bipolar transistor which includes the steps of forming a buried collector, a collector thin film, and a collector sinker on a semiconductor substrate in order, forming a first silicon oxide film, a base electrode polysilicon layer, a nitride film, and an oxidation film on a resulting substrate exposing the first silicon oxidation film, forming a spacer insulation film at the lateral side of the exposed region, and defining an activation region, exposing the collector thin film of the activation region using a mask, and forming an auxiliary lateral film for an isolation of the device, forming a selective collector region by ion-implantating a dopant to the activation region which is limited by the auxiliary lateral film, removing the auxiliary lateral film, etching the exposed portion in an anisotropic etching method, and forming a shallow trench for a device isolation, forming a polysilicon lateral film to have a height which is the same as the height of the base electrode polysilicon layer on the shallow trench, and forming a self-aligned base.

Abstract translation: 一种用于制造异质结双极晶体管的改进方法，其包括以下步骤：在半导体衬底上形成掩埋集电极，集电极薄膜和集电极沉降片，以形成第一氧化硅膜，基极多晶硅层，氮化物 在所得到的基板上暴露第一硅氧化膜的氧化膜，在暴露区域的侧面形成间隔绝缘膜，并限定激活区域，使用掩模曝光激活区域的集电极薄膜， 并形成用于隔离器件的辅助横向膜，通过将离子注入到由辅助侧膜限制的活化区域的掺杂剂形成选择性集电极区域，去除辅助横向膜，在各向异性层中蚀刻暴露部分 蚀刻方法，以及形成用于器件隔离的浅沟槽，形成多晶硅侧膜以具有s的高度 ame作为浅沟槽上的基极多晶硅层的高度，并形成自对准基底。

公开(公告)号：US06562688B2

公开(公告)日：2003-05-13

申请号：US09747761

申请日：2000-12-21

Applicant: Tae-Hyeon Han ,  Byung Ryul Ryum ,  Soo-Min Lee ,  Deok-Ho Cho

Inventor： Tae-Hyeon Han ,  Byung Ryul Ryum ,  Soo-Min Lee ,  Deok-Ho Cho

IPC: H01L21331

CPC classification number: H01L29/66287 ,  H01L29/66242

Abstract: Disclosed are a method for manufacturing a homojunction or heterojunction bipolar device and a structure of the bipolar device manufactured by the method. The method comprises steps of forming a collector on a substrate including a buried collector to be contacted with the buried collector and protruded in the form of an island; depositing a collector dielectric film on the substrate on which the collector is formed; removing a protruded portion of the collector dielectric film covering the substrate; depositing a first semiconductor electrode layer on the substrate including the collector protruded over the collector dielectric film and flatting a surface of the first semiconductor electrode to expose only the collector formed of a semiconductor material and the first semiconductor electrode; and growing a base thin film including one of silicon and silicon-germanium on the substrate on which only the semiconductor material is exposed, thereby preventing the non-uniformity of a thickness of the base thin film, a contain rate of an impurity and a germanium distribution by the loading effect.

Abstract translation: 公开了用于制造均质结或异质结双极器件的方法和通过该方法制造的双极器件的结构。 该方法包括以下步骤：在包括与埋藏式收集器接触并以岛形式突出的埋地收集器的基板上形成集电器; 在其上形成集电极的基板上沉积集电极电介质膜; 去除覆盖所述基板的所述集电极电介质膜的突出部分; 在包括集电极电介质膜上的集电体的基板上沉积第一半导体电极层，使第一半导体电极的表面平坦化，仅露出由半导体材料形成的集电体和第一半导体电极; 并且在仅在其上仅露出半导体材料的基板上生长包括硅和硅锗之一的基底薄膜，从而防止基底薄膜的厚度不均匀，杂质含量和锗的含量 通过负载效应分配。

公开(公告)号：US5874347A

公开(公告)日：1999-02-23

申请号：US688283

申请日：1996-07-29

Applicant: Byung-Ryul Ryum ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Deok-Ho Cho ,  Jin-Young Kang

Inventor： Byung-Ryul Ryum ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Deok-Ho Cho ,  Jin-Young Kang

IPC: H01L21/316 ,  H01L21/32 ,  H01L21/76 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/32 ,  H01L21/76202

Abstract: Disclosed is a device isolating method of a semiconductor device, comprising the steps of sequentially forming a pad oxide film, a polysilicon film and an insulating layer, on a silicon substrate, said insulating layer being composed of a first silicon oxide film, a nitride film and a second silicon oxide film formed sequentially on the polysilicon film; defining active and inactive regions by using a patterned photomask; removing the insulating layer only on the inactive region so as to expose a surface of the polysilicon film; forming a side wall at both edges of the insulating layer on the active region, said side wall being composed of a nitride film; depositing a third silicon oxide film on the surface of the polysilicon film; removing the side wall and etching the substrate to a predetermined depth to form a trench; filling an insulating material into the trench and depositing it up to the second silicon oxide so as to form an insulating film for isolating; simultaneously removing the second silicon oxide film and the silicon oxide film and removing the polysilicon film only the inactive region; performing a thermal oxidation to form a field oxide film on the inactive region; and sequentially removing the isolating layer and the polysilicon film formed on the active region. Because the active region is defined using an insulator-filled shallow trench before performing thermal oxidation, no oxygen is penetrated into the active region during the thermal oxidation, whereby a field oxide film can be formed without occurrence of a Bird's beak.

Abstract translation: 公开了一种半导体器件的器件隔离方法，包括以下步骤：在硅衬底上顺序形成衬垫氧化膜，多晶硅膜和绝缘层，所述绝缘层由第一氧化硅膜，氮化膜 以及顺序地形成在所述多晶硅膜上的第二氧化硅膜; 通过使用图案化的光掩模来定义有源和非活性区域; 仅在非活性区域上去除绝缘层，以暴露多晶硅膜的表面; 在有源区域上的绝缘层的两个边缘处形成侧壁，所述侧壁由氮化物膜构成; 在所述多晶硅膜的表面上沉积第三氧化硅膜; 去除侧壁并将衬底蚀刻到预定深度以形成沟槽; 将绝缘材料填充到沟槽中并将其沉积到第二氧化硅上，以形成用于隔离的绝缘膜; 同时去除第二氧化硅膜和氧化硅膜，并且仅去除多晶硅膜的非活性区域; 进行热氧化以在非活性区域上形成场氧化物膜; 并依次去除形成在有源区上的隔离层和多晶硅膜。 由于在进行热氧化之前使用绝缘子填充的浅沟槽限定有源区域，所以在热氧化期间没有氧气渗透到有源区域中，由此可以形成场氧化膜而不发生鸟喙。

公开(公告)号：US5696007A

公开(公告)日：1997-12-09

申请号：US729840

申请日：1996-10-15

Applicant: Byung-Ryul Ryum ,  Tae-Hyeon Han ,  Deok-Ho Cho ,  Soo-Min Lee ,  Kwang-Eui Pyun

Inventor： Byung-Ryul Ryum ,  Tae-Hyeon Han ,  Deok-Ho Cho ,  Soo-Min Lee ,  Kwang-Eui Pyun

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/165 ,  H01L29/70 ,  H01L29/732 ,  H01L29/737 ,  H01L21/265

CPC classification number: H01L29/66242 ,  H01L29/7378 ,  Y10S148/072

Abstract: The invention relates to a method for manufacturing a super self-aligned heterojunction bipolar transistor which is capable of miniaturizing an element, simplifying the process step thereof by employing a selective collector epitaxial growth and a polycide base electrode without using a trench for isolating between elements, thereby enhancing the performance thereof, which comprises the steps of: forming sequently a first oxidation film, an electrically conducting thin film and a second oxidation film on top of a substrate; patterning the second oxidation film and the conducting thin film to form a preliminary spacer; removing an exposed portion of the first oxidation film, and selectively growing a collector layer; oxidizing the collector layer to form a thermal oxidation film, and removing the preliminary spacer; depositing a polysilicon and forming a silicon oxidation film and a polysilicon spacer on the second oxidation film and the removed portion of the preliminary spacer, respectively; exposing the base thin film, the spacer and the collector layer to form a SiGe/Si layer; forming a base electrode on the SiGe/Si layer; exposing a portion of the first oxidation film and forming a third oxidation film; exposing a surface of the SiGe/Si layer and forming a oxidation spacer on sides of an etched portion, then self-aligning the emitter and the emitter electrode; and performing a metal wiring process.

Abstract translation: 本发明涉及一种能够使元件小型化的超自对准异质结双极晶体管的制造方法，通过采用选择性集电体外延生长和多选择性基极电极简化其工艺步骤，而不使用用于隔离元件之间的沟槽， 从而提高其性能，其包括以下步骤：在衬底的顶部上顺次形成第一氧化膜，导电薄膜和第二氧化膜; 图案化第二氧化膜和导电薄膜以形成预备间隔物; 去除第一氧化膜的暴露部分，并选择性地生长集电体层; 氧化所述集电体层以形成热氧化膜，并除去所述预备间隔物; 在所述第二氧化膜上分别沉积多晶硅并形成硅氧化膜和多晶硅间隔物和所述预备间隔物的去除部分; 暴露基底薄膜，间隔物和集电极层以形成SiGe / Si层; 在SiGe / Si层上形成基极; 暴露第一氧化膜的一部分并形成第三氧化膜; 暴露SiGe / Si层的表面并在蚀刻部分的侧面上形成氧化间隔物，然后自发对准发射极和发射极; 并执行金属布线处理。

公开(公告)号：US5496745A

公开(公告)日：1996-03-05

申请号：US358825

申请日：1994-12-19

Applicant: Byung-Ryul Ryum ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Deok-Ho Cho ,  Seong-Hearn Lee ,  Jin-Young Kang

Inventor： Byung-Ryul Ryum ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Deok-Ho Cho ,  Seong-Hearn Lee ,  Jin-Young Kang

IPC: H01L21/331 ,  H01L21/762 ,  H01L21/265

CPC classification number: H01L29/66287 ,  H01L21/76224 ,  Y10S148/01 ,  Y10S148/011 ,  Y10S148/072

Abstract: Disclosed is a fabrication of a bipolar transistor using an enhanced trench isolation so as to improve integration and performance thereof, comprising the steps of sequentially etching back portions corresponding to a trench using a trench forming mask to a predetermined depth of the buried collector to form the trench; filling an isolation insulating layer into the trench; polishing the isolation insulating layer up to a surface of the silicon oxide layer; sequentially forming a second insulating layer on the isolating insulating layer and the silicon oxide layer; removing the first polysilicon layer and the first insulating layer formed on an inactive region other than an active region defined by the trench; thermal-oxidizing the collector layer formed on the inactive region to form a thermal oxide layer; removing the second insulating layer and sequentially forming a third polysilicon, a third insulating layer and a second nitride layer; etching back layers formed on a portion of the first insulating layer to form an opening in the active region; forming a first side wall on both edges of the opening and removing the first insulating layer; forming an intrinsic base at a region where the first insulating layer is removed to electrically connect the intrinsic base with an extrinsic base in self-alignment; forming a second side wall on both sides of the first side wall; and forming an emitter layer on the intrinsic base.

Abstract translation: 公开了使用增强的沟槽隔离来改善其集成和性能的双极晶体管的制造，其包括以下步骤：使用沟槽形成掩模将对应于沟槽的部分依次蚀刻到掩埋集电极的预定深度，以形成 沟; 将隔离绝缘层填充到沟槽中; 将隔离绝缘层抛光直到氧化硅层的表面; 在隔离绝缘层和氧化硅层上依次形成第二绝缘层; 除去形成在除了由沟槽限定的有源区域之外的非活性区域上的第一多晶硅层和第一绝缘层; 对形成在非活性区域上的集电体层进行热氧化以形成热氧化物层; 去除所述第二绝缘层并顺序地形成第三多晶硅，第三绝缘层和第二氮化物层; 蚀刻形成在所述第一绝缘层的一部分上的层以在所述有源区中形成开口; 在所述开口的两个边缘上形成第一侧壁并移除所述第一绝缘层; 在去除所述第一绝缘层的区域上形成本征基极以使所述本征基极与自对准的外部基极电连接; 在所述第一侧壁的两侧上形成第二侧壁; 并在本征基底上形成发射极层。

公开(公告)号：US06462397B2

公开(公告)日：2002-10-08

申请号：US10027583

申请日：2001-10-22

Applicant: Byung Ryul Ryum ,  Tae Hyeon Han ,  Soo Min Lee ,  Deok Ho Cho

Inventor： Byung Ryul Ryum ,  Tae Hyeon Han ,  Soo Min Lee ,  Deok Ho Cho

IPC: H01L27082

CPC classification number: H01L29/66287 ,  H01L29/66242

Abstract: The present invention is related to a bipolar transistor in which the in-situ doped epitaxial Si or SiGe base layer is used instead of using an ion-implanted Si base, in order to achieve higher cutoff frequency. The SiGe base having the narrower energy bandgap than the Si emitter allows to enhance the current gain, the cutoff frequency(fT), and the maximum oscillation frequency (fmax). The narrow bandgap SiGe base also allows to have higher base doping concentration. As a result, the intrinsic base resistance is lowered and the noise figure is thus lowered. Parasitic base resistance is also minimized by using a metallic silicide base ohmic electrode. The present invention is focused on low cost, high repeatability and reliability by simplifying the manufacturing process step.

Abstract translation: 本发明涉及一种双极晶体管，其中使用原位掺杂的外延Si或SiGe基层代替使用离子注入的Si基，以便实现更高的截止频率。 具有比Si发射器更窄的能带隙的SiGe基极允许增强电流增益，截止频率（fT）和最大振荡频率（fmax）。 窄带隙SiGe基极还允许具有较高的基极掺杂浓度。 结果，本征基极电阻降低，噪声系数降低。 通过使用金属硅化物基极欧姆电极也使寄生基极电阻最小化。 通过简化制造工艺步骤，本发明集中在低成本，高重复性和可靠性上。

公开(公告)号：US6140195A

公开(公告)日：2000-10-31

申请号：US213868

申请日：1998-12-17

Applicant: Byung-Ryul Ryum ,  Soo-Min Lee ,  Deok-Ho Cho ,  Tae-Hyeon Han

Inventor： Byung-Ryul Ryum ,  Soo-Min Lee ,  Deok-Ho Cho ,  Tae-Hyeon Han

IPC: H01L21/328 ,  H01L21/331 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/0649 ,  H01L29/0821 ,  H01L29/66265 ,  H01L29/66272

Abstract: The present invention provides a collector device in a bipolar device, having a lateral collector structure on a buried oxide layer. This collector has a high breakdown voltage for high power and operating at a high speed, by isolating a horizontal collector from a substrate by a buried oxide film and horizontally connecting a buried collector to a collector. The buried collector film is formed on the buried insulating film, surrounding the collector film and being horizontally connected to the collector film.

Abstract translation: 本发明提供一种在双极器件中的集电极器件，其在掩埋氧化物层上具有横向收集器结构。 该集电极具有高功率的高击穿电压并以高速工作，通过埋入氧化膜将水平集电器与衬底隔离并将埋入式收集器水平连接到集电器。 埋置的集电体膜形成在埋入绝缘膜上，围绕集电体膜并且与集电体膜水平连接。

公开(公告)号：US06124614A

公开(公告)日：2000-09-26

申请号：US233329

申请日：1999-01-20

Applicant: Byung-Ryul Ryum ,  Soo-Min Lee ,  Deok-Ho Cho ,  Tae-Hyeon Han

Inventor： Byung-Ryul Ryum ,  Soo-Min Lee ,  Deok-Ho Cho ,  Tae-Hyeon Han

IPC: H01L27/06 ,  H01L21/336 ,  H01L29/10 ,  H01L29/417 ,  H01L29/45 ,  H01L27/01 ,  H01L21/249

CPC classification number: H01L29/66477 ,  H01L29/1054 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66651

Abstract: The present invention relates to a metal silicon field effect transistor (MOSFET), and more particularly to a MOSFET, using a Si or SiGe channel to effectively adjust threshold voltage. The transistor according to the present invention can solve the problems, such as the punch-through caused by the short distance between the source region and the drain region, the decrease of the breakdown voltage between the source region and the drain region and the leakage current flowing into the bulk region beneath the channel due to the drain-induced barrier lowering. Furthermore, because the source region and the drain region are isolated from the semiconductor substrate by the lower insulation layer, the removal of the parasite junction capacitor speed up the transistor.

Abstract translation: 本发明涉及金属硅场效应晶体管（MOSFET），更具体地说，涉及一种使用Si或SiGe沟道来有效调节阈值电压的MOSFET。 根据本发明的晶体管可以解决诸如源极区域和漏极区域之间的短距离引起的穿通，源极区域和漏极区域之间的击穿电压的降低以及漏电流的问题 由于漏极引起的屏障降低，流入通道下方的体区域。 此外，由于源极区域和漏极区域通过下部绝缘层与半导体衬底隔离，因此去除寄生电容器电容器加速了晶体管。

公开(公告)号：US5484737A

公开(公告)日：1996-01-16

申请号：US357244

申请日：1994-12-13

Applicant: Byung-Ryul Ryum ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Deok-Ho Cho ,  Seong-Hearn Lee ,  Jin-Young Kang

Inventor： Byung-Ryul Ryum ,  Tae-Hyeon Han ,  Soo-Min Lee ,  Deok-Ho Cho ,  Seong-Hearn Lee ,  Jin-Young Kang

IPC: H01L21/331 ,  H01L29/732 ,  H01L29/737 ,  H01L21/8222

CPC classification number: H01L29/66242 ,  H01L29/732 ,  H01L29/7378 ,  Y10S148/059 ,  Y10S148/067

Abstract: Disclosed is a fabrication of a bipolar transistor with a super self-aligned vertical structure in which emitter, base and collector are vertically self-aligned, the fabrication method comprising the steps of forming a conductive buried collector region in a silicon substrate by using ion-implantation of an impurity and thermal-annealing; sequentially forming several layers; selectively removing the nitride and polysilicon layers to form a pattern; sequentially forming a silicon oxide layer, a third layer and a silicon oxide layer thereon; forming a patterned photoresist layer thereon to define active and inactive regions and removing several layers on the active region to form an opening; forming a side wall on both sides of the opening; forming a collector on a surface portion of the buried collector region up to a lower surface of the polysilicon layer; removing the side wall and the third nitride layer to expose a side surface of the second polysilicon layer; selectively forming a base on an upper surface of the collector including a side surface of the polysilicon layer; forming side wall oxide layer on both sides of the base and the silicon oxide to define an emitter region; forming an emitter on the base; and forming electrodes thereon. In the method, an active region is defined by a photolithography, and thereby a trench isolation acting as factors of lowering in integration and device-performance can be omitted in the method. As a result, fabrication sequence can be simplified and integration can be improved.

Abstract translation: 公开了一种具有超自对准垂直结构的双极晶体管的制造，其中发射极，基极和集电极垂直自对准，所述制造方法包括以下步骤：通过使用离子交换膜在硅衬底中形成导电掩埋集电极区域， 注入杂质和热退火; 依次形成几层; 选择性地去除氮化物和多晶硅层以形成图案; 在其上依次形成氧化硅层，第三层和氧化硅层; 在其上形成图案化的光致抗蚀剂层以限定活性和非活性区域并去除活性区域上的多个层以形成开口; 在开口的两侧形成侧壁; 在所述掩埋集电极区域的表面部分上形成集电体直到所述多晶硅层的下表面; 去除侧壁和第三氮化物层以暴露第二多晶硅层的侧表面; 在所述集电体的上表面上选择性地形成基底，所述基底包括所述多晶硅层的侧表面; 在所述基底和所述氧化硅的两侧上形成侧壁氧化物层以限定发射极区域; 在基底上形成发射体; 并在其上形成电极。 在该方法中，通过光刻法定义有源区，因此可以在该方法中省略作为降低集成度和器件性能的因素的沟槽隔离。 结果，可以简化制造顺序并且可以提高集成。