公开(公告)号：US07262447B2

公开(公告)日：2007-08-28

申请号：US10780699

申请日：2004-02-19

Applicant: Takaaki Negoro ,  Akira Shimizu

Inventor： Takaaki Negoro ,  Akira Shimizu

IPC: H01L29/80 ,  H01L31/112

CPC classification number: H01L29/4983 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/092 ,  H01L29/1045 ,  H01L29/42368 ,  H03K3/0315

Abstract: A semiconductor apparatus includes a MOS transistor having a semiconductor substrate providing as a channel region between a source and a drain. A gate electrode is formed on the semiconductor substrate via a gate oxide film. A threshold voltage of the source side region of the MOS transistor is higher than that of the drain side region in a longitudinal direction of the channel region so that a saturation drain current can be constant and a λ performance can be improved while suppressing channel width and length.

Abstract translation: 半导体装置包括MOS晶体管，其具有提供源极和漏极之间的沟道区域的半导体衬底。 栅电极通过栅极氧化膜形成在半导体衬底上。 MOS晶体管的源侧区域的阈值电压高于沟道区域的纵向方向上的漏极侧区域的阈值电压，使得饱和漏极电流可以是恒定的，并且可以在抑制沟道宽度的同时提高λ性能， 长度。

公开(公告)号：US07242059B2

公开(公告)日：2007-07-10

申请号：US10769817

申请日：2004-02-03

Applicant: Takaaki Negoro ,  Keiji Fujimoto ,  Takeshi Kimura

Inventor： Takaaki Negoro ,  Keiji Fujimoto ,  Takeshi Kimura

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L21/823892 ,  H01L27/0922

Abstract: A semiconductor device includes a P-type semiconductor substrate, a P-channel DMOS transistor, a CMOS transistor. The P-channel DMOS transistor is disposed on the P-type semiconductor substrate and includes a drain formed of the P-type semiconductor substrate and a source formed in the P-type semiconductor substrate on a main surface of the P-type semiconductor substrate. The CMOS transistor is disposed on the P-type semiconductor substrate and includes a P-channel MOS transistor and an N-channel MOS transistor. The P-channel MOS transistor is formed in an N-type region formed in the P-type semiconductor substrate on the main surface of the P-type semiconductor substrate. The N-channel MOS transistor is formed in a P-type region formed in the P-type semiconductor substrate on the main surface of the P-type semiconductor substrate. The P-type region is electrically isolated from the P-type semiconductor substrate by the N-type region.

Abstract translation: 半导体器件包括P型半导体衬底，P沟道DMOS晶体管，CMOS晶体管。 P沟道DMOS晶体管设置在P型半导体衬底上，并且包括由P型半导体衬底形成的漏极和在P型半导体衬底的主表面上形成在P型半导体衬底中的源极。 CMOS晶体管设置在P型半导体衬底上，并且包括P沟道MOS晶体管和N沟道MOS晶体管。 P型MOS晶体管形成在形成在P型半导体衬底的P型半导体衬底的主表面上的N型区域中。 N沟道MOS晶体管形成在P型半导体衬底的形成在P型半导体衬底的P型半导体衬底的主表面上的P型区域中。 P型区域通过N型区域与P型半导体衬底电隔离。

公开(公告)号：US20060138546A1

公开(公告)日：2006-06-29

申请号：US11313640

申请日：2005-12-22

Applicant: Takaaki Negoro ,  Koichi Morino

Inventor： Takaaki Negoro ,  Koichi Morino

IPC: H01L23/62

CPC classification number: G05F1/56

Abstract: A voltage regulator having a MOS transistor driver is disclosed. The voltage regulator comprises a p-channel MOS transistor at a voltage input terminal Vin and a p-channel MOS transistor at a voltage output terminal Vout. A drain of the input side p-channel MOS transistor is connected to the voltage input terminal Vin. A threshold voltage or a voltage lower than the threshold voltage is applied to a gate of the input side p-channel MOS transistor. A drain of the output side p-channel MOS transistor is connected to the voltage output terminal Vout. A current flowing through the input side p-channel MOS transistor drives a voltage regulator circuit and the output side p-channel MOS transistor.

Abstract translation: 公开了一种具有MOS晶体管驱动器的稳压器。 电压调节器包括电压输入端Vin处的p沟道MOS晶体管和电压输出端Vout的p沟道MOS晶体管。 输入侧p沟道MOS晶体管的漏极连接到电压输入端子Vin。 将阈值电压或低于阈值电压的电压施加到输入侧p沟道MOS晶体管的栅极。 输出侧p沟道MOS晶体管的漏极连接到电压输出端子Vout。 流过输入侧p沟道MOS晶体管的电流驱动电压调节器电路和输出侧p沟道MOS晶体管。

公开(公告)号：US20050199951A1

公开(公告)日：2005-09-15

申请号：US11099588

申请日：2005-04-06

Applicant: Akira Shimizu ,  Takaaki Negoro

Inventor： Akira Shimizu ,  Takaaki Negoro

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/94 ,  H01L29/76 ,  H01L21/322

CPC classification number: H01L29/7816 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: A semiconductor device, methods for manufacturing the semiconductor device, and an integrated circuit including the semiconductor device are disclosed. The semiconductor device includes an LDMOS transistor and a MOS transistor, both formed simultaneously on a same substrate. The gate electrodes and the gate oxide layers of the LDMOS and the MOS are formed independently from one another. The source and drain regions of the LDMOS and the MOS are respectively formed in a self-aligned manner. In this way, the LDMOS and the MOS can be formed, in an effective manner, while sustaining the respective desired characteristics.

Abstract translation: 公开了半导体器件，半导体器件的制造方法和包括半导体器件的集成电路。 半导体器件包括同时在同一衬底上形成的LDMOS晶体管和MOS晶体管。 LDMOS和MOS的栅电极和栅氧化层彼此独立地形成。 LDMOS和MOS的源极和漏极区分别以自对准的方式形成。 以这种方式，可以以有效的方式在保持各自期望特性的同时形成LDMOS和MOS。