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    HIERARCHICAL WORK SCHEDULING
    52.
    发明申请
    HIERARCHICAL WORK SCHEDULING 有权

    公开(公告)号：US20250068464A1

    公开(公告)日：2025-02-27

    申请号：US18940931

    申请日：2024-11-08

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Matthaeus G. Chajdas ,  Christopher J. Brennan ,  Michael Mantor ,  Robert W. Martin ,  Nicolai Haehnle

    IPC: G06F9/48

    Abstract: A method for hierarchical work scheduling includes consuming a work item at a first scheduling domain having a local scheduler circuit and one or more workgroup processing elements. Consuming the work item produces a set of new work items. Subsequently, the local scheduler circuit distributes at least one new work item of the set of new work items to be executed locally at the first scheduling domain. If the local scheduler circuit of the first scheduling domain determines that the set of new work items includes one or more work items that would overload the first scheduling domain with work if scheduled for local execution, those work items are distributed to the next higher-level scheduler circuit in a scheduling domain hierarchy for redistribution to one or more other scheduling domains.

    STREAMING WAVE COALESCER CIRCUIT
    53.
    发明申请
    STREAMING WAVE COALESCER CIRCUIT 有权

    公开(公告)号：US20250068429A1

    公开(公告)日：2025-02-27

    申请号：US18536982

    申请日：2023-12-12

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： John Stephen Junkins ,  Christopher J. Brennan ,  Ian Richard Beaumont ,  Kellie Marks ,  Matthaeus G. Chajdas ,  Max Oberberger ,  Michael John Bedy ,  Michael Mantor ,  Sean Keely

    IPC: G06F9/38

    Abstract: A Streaming Wave Coalescer (SWC) circuit stores a first set of state values associated with a first subset of threads of a first wave in a bin based on each of the first subset of threads including a first set of instructions to be executed. A second set of state values associated with a second subset of threads of a second wave is stored in the bin based on each of the second subset of threads including the first set of instructions to be executed and based on the first wave and the second wave both being associated with a hard key. A third wave is formed from the threads of the first subset and the second subset and is emitted for execution. As a result of reorganizing the threads and reconstituting a different wave, thread divergence of waves sent for execution is reduced.

    Processing unit with small footprint arithmetic logic unit
    54.
    发明授权
    Processing unit with small footprint arithmetic logic unit 有权

    公开(公告)号：US12217021B2

    公开(公告)日：2025-02-04

    申请号：US18219268

    申请日：2023-07-07

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Bin He ,  Shubh Shah ,  Michael Mantor

    IPC: G06F7/57 ,  G06F17/16 ,  G06N3/08

    Abstract: A parallel processing unit employs an arithmetic logic unit (ALU) having a relatively small footprint, thereby reducing the overall power consumption and circuit area of the processing unit. To support the smaller footprint, the ALU includes multiple stages to execute operations corresponding to a received instruction. The ALU executes at least one operation at a precision indicated by the received instruction, and then reduces the resulting data of the at least one operation to a smaller size before providing the results to another stage of the ALU to continue execution of the instruction.

    ADAPTIVE MULTIMODAL FUSING FOR NON-PLAYER CHARACTER GENERATION AND CONFIGURATION
    55.
    发明申请
    ADAPTIVE MULTIMODAL FUSING FOR NON-PLAYER CHARACTER GENERATION AND CONFIGURATION 有权

    公开(公告)号：US20240424407A1

    公开(公告)日：2024-12-26

    申请号：US18749065

    申请日：2024-06-20

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Karthik Mohan Kumar ,  Michael Mantor ,  Pedro Antonio Pena ,  Archana Ramalingam

    IPC: A63F13/67 ,  G06F40/284

    Abstract: Systems and techniques for generating and animating non-player characters (NPCs) within virtual digital environments are provided. Multimodal input data is received that comprises a plurality of input modalities for interaction with an NPC having a set of body features and a set of facial features. The multimodal input data is processed through one or more neural networks to generate animation sequences for both the body features and facial features of the NPC. Generating such animation sequences includes disentangling the multimodal input data to generate substantially disentangled latent representations, combining these representations with the multimodal input data, and using a large-language model (LLM) to generate speech data for the NPC. Further processing using reverse diffusion generates face vertex displacement data and joint trajectory data based on the combined representation and generated speech data. The face vertex displacement data, joint trajectory data, and speech data are used to produce an animated representation of the NPC, which is then provided to environment-specific adapters to animate the NPC within a virtual digital environment.

    HIERARCHICAL WORK SCHEDULING
    56.
    发明公开
    HIERARCHICAL WORK SCHEDULING 审中-公开

    公开(公告)号：US20240111578A1

    公开(公告)日：2024-04-04

    申请号：US17957714

    申请日：2022-09-30

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Matthaeus G. Chajdas ,  Christopher J. Brennan ,  Michael Mantor ,  Robert W. Martin ,  Nicolai Haehnle

    IPC: G06F9/48

    CPC classification number: G06F9/4881

    Abstract: A method for hierarchical work scheduling includes consuming a work item at a first scheduling domain having a local scheduler circuit and one or more workgroup processing elements. Consuming the work item produces a set of new work items. Subsequently, the local scheduler circuit distributes at least one new work item of the set of new work items to be executed locally at the first scheduling domain. If the local scheduler circuit of the first scheduling domain determines that the set of new work items includes one or more work items that would overload the first scheduling domain with work if scheduled for local execution, those work items are distributed to the next higher-level scheduler circuit in a scheduling domain hierarchy for redistribution to one or more other scheduling domains.

    Precise suspend and resume of workloads in a processing unit
    57.
    发明授权
    Precise suspend and resume of workloads in a processing unit 有权

    公开(公告)号：US11609791B2

    公开(公告)日：2023-03-21

    申请号：US15828059

    申请日：2017-11-30

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Anirudh R. Acharya ,  Michael Mantor

    IPC: G06F9/50 ,  G06T1/20 ,  G06F9/52 ,  G06F9/48

    Abstract: A first workload is executed in a first subset of pipelines of a processing unit. A second workload is executed in a second subset of the pipelines of the processing unit. The second workload is dependent upon the first workload. The first and second workloads are suspended and state information for the first and second workloads is stored in a first memory in response to suspending the first and second workloads. In some cases, a third workload executes in a third subset of the pipelines of the processing unit concurrently with executing the first and second workloads. In some cases, a fourth workload is executed in the first and second pipelines after suspending the first and second workloads. The first and second pipelines are resumed on the basis of the stored state information in response to completion or suspension of the fourth workload.

    DUAL VECTOR ARITHMETIC LOGIC UNIT
    59.
    发明申请
    DUAL VECTOR ARITHMETIC LOGIC UNIT 有权

    公开(公告)号：US20220188076A1

    公开(公告)日：2022-06-16

    申请号：US17121354

    申请日：2020-12-14

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Bin He ,  Brian Emberling ,  Mark Leather ,  Michael Mantor

    IPC: G06F7/57 ,  G06F17/16 ,  G06F9/38 ,  G06T1/20

    Abstract: A processing system executes wavefronts at multiple arithmetic logic unit (ALU) pipelines of a single instruction multiple data (SIMD) unit in a single execution cycle. The ALU pipelines each include a number of ALUs that execute instructions on wavefront operands that are collected from vector general process register (VGPR) banks at a cache and output results of the instructions executed on the wavefronts at a buffer. By storing wavefronts supplied by the VGPR banks at the cache, a greater number of wavefronts can be made available to the SIMD unit without increasing the VGPR bandwidth, enabling multiple ALU pipelines to execute instructions during a single execution cycle.

    Selective prefetching in multithreaded processing units
    60.
    发明授权
    Selective prefetching in multithreaded processing units 有权

    公开(公告)号：US11226819B2

    公开(公告)日：2022-01-18

    申请号：US15818304

    申请日：2017-11-20

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Brian Emberling ,  Michael Mantor

    IPC: G06F9/30 ,  G06F12/0862 ,  G06F12/0811

    Abstract: A processing unit includes a plurality of processing elements and one or more caches. A first thread executes a program that includes one or more prefetch instructions to prefetch information into a first cache. Prefetching is selectively enabled when executing the first thread on a first processing element dependent upon whether one or more second threads previously executed the program on the first processing element. The first thread is then dispatched to execute the program on the first processing element. In some cases, a dispatcher receives the first thread four dispatching to the first processing element. The dispatcher modifies the prefetch instruction to disable prefetching into the first cache in response to the one or more second threads having previously executed the program on the first processing element.

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