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公开(公告)号：US10579388B2
公开(公告)日：2020-03-03
申请号：US16040224
申请日：2018-07-19
Applicant: Advanced Micro Devices, Inc.
Inventor： Robert Scott Hartog , Mark Leather , Michael Mantor , Rex McCrary , Sebastien Nussbaum , Philip J. Rogers , Ralph Clay Taylor , Thomas Woller
Abstract: A method for use in a processor for arbitrating between multiple processes to select wavefronts for execution on a shader core is provided. The processor includes a compute pipeline configured to issue wavefronts to the shader core for execution, a hardware queue descriptor associated with the compute pipeline, and the shader core. The shader core is configured to execute work for the compute pipeline corresponding to a first memory queue descriptor executed using data for the first memory queue descriptor that is loaded into a first hardware queue descriptor. The processor is configured to detect a context switch condition, and, responsive to the context switch condition, perform a context switch operation including loading data for a second memory queue descriptor into the first hardware queue descriptor. The shader core is configured to execute work corresponding to the second memory queue descriptor that is loaded into the first hardware queue descriptor.
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公开(公告)号：US10242420B2
公开(公告)日：2019-03-26
申请号：US15362230
申请日：2016-11-28
Applicant: Advanced Micro Devices, Inc.
Inventor： Robert Scott Hartog , Ralph Clayton Taylor , Michael Mantor , Kevin John McGrath , Sebastien Nussbaum , Nuwan Jayasena , Rex McCrary , Mark Leather , Philip J. Rogers , Thomas Woller
Abstract: Methods and apparatus are described. A method includes an accelerated processing device running a process. When a maximum time interval during which the process is permitted to run expires before the process completes, the accelerated processing device receives an operating-system-initiated instruction to stop running the process. The accelerated processing device stops the process from running in response to the received operating-system-initiated instruction.
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公开(公告)号：US09686536B2
公开(公告)日：2017-06-20
申请号：US14282330
申请日：2014-05-20
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Eric Rentschler , Sebastien Nussbaum
CPC classification number: H04N17/00 , G06F3/1423 , G06F13/28 , G09G5/006 , G09G2350/00 , G09G2370/047 , G09G2370/10 , H04N1/32571 , H04N17/04 , H04N21/43632 , H04N21/44231 , H04N21/6582
Abstract: A video device having data lanes and a method of operating the video device includes generating performance monitoring and/or debug data in response to the operation of the video device. The generated data is sampled from component of the video device operating in various clocking domain. The data sampled from the components is combined into a unified stream which is independent of the various clocking domain. The unified stream is transmitted across one more data lanes of a video link along with corresponding audio and/or video data in real time.
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公开(公告)号：US20180081830A1
公开(公告)日：2018-03-22
申请号：US15270708
申请日：2016-09-20
Applicant: Advanced Micro Devices, Inc.
Inventor： David Kaplan , Sebastien Nussbaum
IPC: G06F12/14 , G06F12/1009
CPC classification number: G06F12/1483 , G06F12/1009 , G06F2212/1052
Abstract: A processing system includes one or more processing units, a memory including a protected region, and a hardware security module. The hardware security module is configured to selectively modify a page table stored in the protected region of the memory in response to write or modify requests from the at least one processing unit. In some variations, the hardware security module can modify the page table in response to verifying that a security criterion is met by the requested modification of the page table. The hardware security module can also access a code signature in response to a request to mark a page in the page table as eligible for execution and selectively mark the page as executable based on whether the code signature matches a signature of code stored in the page.
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公开(公告)号：US09052885B2
公开(公告)日：2015-06-09
申请号：US13723276
申请日：2012-12-21
Applicant: Advanced Micro Devices, Inc.
Inventor： Samuel D. Naffziger , Michael Osborn , Sebastien Nussbaum
Abstract: A method and apparatus using temperature margin to balance performance with power allocation. Nominal, middle and high power levels are determined for compute elements. A set of temperature thresholds are determined that drive the power allocation of the compute elements towards a balanced temperature profile. For a given workload, temperature differentials are determined for each of the compute elements relative the other compute elements, where the temperature differentials correspond to workload utilization of the compute element. If temperature overhead is available, and a compute element is below a temperature threshold, then particular compute elements are allocated power to match or drive toward the balanced temperature profile.
Abstract translation: 使用温度裕度平衡性能与功率分配的方法和装置。 对于计算元素确定标称，中等和高功率电平。 确定一组温度阈值，其将计算元件的功率分配驱动到平衡温度分布。 对于给定的工作负载，相对于其他计算元件，每个计算元素确定温差，其中温差对应于计算元件的工作负载利用率。 如果温度开销可用，并且计算元件低于温度阈值，则特定计算元件被分配功率以匹配或驱动平衡温度曲线。
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Patent Agency Ranking
公开(公告)号：US20140340527A1
公开(公告)日：2014-11-20
申请号：US14282330
申请日：2014-05-20
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Winthrop Wu , Sebastien Nussbaum
IPC: H04N17/00
CPC classification number: H04N17/00 , G06F3/1423 , G06F13/28 , G09G5/006 , G09G2350/00 , G09G2370/047 , G09G2370/10 , H04N1/32571 , H04N17/04 , H04N21/43632 , H04N21/44231 , H04N21/6582
Abstract: A video device having data lanes and a method of operating the video device includes generating performance monitoring and/or debug data in response to the operation of the video device. The generated data is sampled from component of the video device operating in various clocking domain. The data sampled from the components is combined into a unified stream which is independent of the various clocking domain. The unified stream is transmitted across one more data lanes of a video link along with corresponding audio and/or video data in real time.
Abstract translation: 具有数据通道的视频设备和操作视频设备的方法包括响应于视频设备的操作而产生性能监视和/或调试数据。 所生成的数据从在各种计时域中操作的视频设备的组件中进行采样。 从组件采集的数据被组合成独立于各种时钟域的统一流。 统一的数据流通过视频链路的多个数据通道连同相应的音频和/或视频数据实时传输。
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公开(公告)号：US09870473B2
公开(公告)日：2018-01-16
申请号：US14529278
申请日：2014-10-31
Applicant: Advanced Micro Devices, Inc.
Inventor： Benjamin Tsien , Denis Rystsov , Sebastien Nussbaum
CPC classification number: G06F21/57 , G06F1/26 , G06F1/3206 , G06F1/3237 , G06F1/3287 , G06F21/50 , G06F21/81 , Y02B70/123 , Y02B70/126 , Y02D10/128 , Y02D10/171
Abstract: The present disclosure presents methods and apparatuses for controlling a power state, which may include a C-state, of one or more processing cores of a processor. In an aspect, an example method of securing a power state change of a processor is presented, the method including the steps of receiving a power state change request from the processor, the processor having a plurality of potential power states each including an operating power profile; determining a power state change request mode associated with the processor; forwarding the power state change request to a security processor where the power state change request mode is a one-time request mode; receiving a power state change request response from the security processor in response to the request; and adjusting the current power state of the processor to the target power state where the power state change request response comprises a power state change approval.
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8.发明申请公开(公告)号：US20150121520A1
公开(公告)日：2015-04-30
申请号：US14529278
申请日：2014-10-31
Applicant: Advanced Micro Devices, Inc.
Inventor： Benjamin Tsien , Denis Rystsov , Sebastien Nussbaum
CPC classification number: G06F21/57 , G06F1/26 , G06F1/3206 , G06F1/3237 , G06F1/3287 , G06F21/50 , G06F21/81 , Y02B70/123 , Y02B70/126 , Y02D10/128 , Y02D10/171
Abstract: The present disclosure presents methods and apparatuses for controlling a power state, which may include a C-state, of one or more processing cores of a processor. In an aspect, an example method of securing a power state change of a processor is presented, the method including the steps of receiving a power state change request from the processor, the processor having a plurality of potential power states each including an operating power profile; determining a power state change request mode associated with the processor; forwarding the power state change request to a security processor where the power state change request mode is a one-time request mode; receiving a power state change request response from the security processor in response to the request; and adjusting the current power state of the processor to the target power state where the power state change request response comprises a power state change approval.
Abstract translation: 本公开提供了用于控制处理器的一个或多个处理核心的功率状态（其可以包括C状态）的方法和装置。 在一方面，提出了一种确保处理器的电源状态改变的示例性方法，所述方法包括以下步骤：从处理器接收电力状态改变请求，所述处理器具有多个潜在功率状态，每个包括工作功率分布 ; 确定与所述处理器相关联的功率状态改变请求模式; 将所述电力状态改变请求转发到所述电力状态改变请求模式是一次性请求模式的安全处理器; 响应于该请求从安全处理器接收电力状态改变请求响应; 以及将所述处理器的当前功率状态调整到所述电力状态改变请求响应包括电力状态改变许可的所述目标电力状态。
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公开(公告)号：US20180321946A1
公开(公告)日：2018-11-08
申请号：US16040224
申请日：2018-07-19
Applicant: Advanced Micro Devices, Inc.
Inventor： Robert Scott Hartog , Mark Leather , Michael Mantor , Rex McCrary , Sebastien Nussbaum , Philip J. Rogers , Ralph Clay Taylor , Thomas Woller
CPC classification number: G06F9/3851 , G06F9/3879 , G06F9/4881 , G06T1/20
Abstract: A method for use in a processor for arbitrating between multiple processes to select wavefronts for execution on a shader core is provided. The processor includes a compute pipeline configured to issue wavefronts to the shader core for execution, a hardware queue descriptor associated with the compute pipeline, and the shader core. The shader core is configured to execute work for the compute pipeline corresponding to a first memory queue descriptor executed using data for the first memory queue descriptor that is loaded into a first hardware queue descriptor. The processor is configured to detect a context switch condition, and, responsive to the context switch condition, perform a context switch operation including loading data for a second memory queue descriptor into the first hardware queue descriptor. The shader core is configured to execute work corresponding to the second memory queue descriptor that is loaded into the first hardware queue descriptor.
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公开(公告)号：US20140344947A1
公开(公告)日：2014-11-20
申请号：US14282442
申请日：2014-05-20
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Nathan Kalyanasundharam , Sebastien Nussbaum
IPC: G06F21/60
CPC classification number: G06F21/62
Abstract: A method and apparatus is provided for improving security of context information of processing circuitry of a processing device. In one example, the method and apparatus stores context information of the processing circuitry on an external storage medium at a first location as part of the processing circuitry entering a first power state, and stores the context information of the processing circuitry on the storage medium at a second location as part of the processing circuitry entering a second, later and different power state.
Abstract translation: 提供了一种用于提高处理装置的处理电路的上下文信息的安全性的方法和装置。 在一个示例中，该方法和装置将处理电路的上下文信息存储在第一位置的外部存储介质上，作为处理电路进入第一功率状态的一部分，并将处理电路的上下文信息存储在存储介质上 作为进入第二，稍后和不同功率状态的处理电路的一部分的第二位置。
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