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    Uniquification and parent-child constructs for 1xN VLSI design
    53.
    发明授权
    Uniquification and parent-child constructs for 1xN VLSI design 有权
    1xN VLSI设计的唯一性和父子结构

    公开(公告)号：US08156458B2

    公开(公告)日：2012-04-10

    申请号：US12201685

    申请日：2008-08-29

    申请人： Matthew W. Baker ,  Benjamin J. Bowers ,  Anthony Correale, Jr. ,  Irfan Rashid ,  Paul M. Steinmetz

    发明人： Matthew W. Baker ,  Benjamin J. Bowers ,  Anthony Correale, Jr. ,  Irfan Rashid ,  Paul M. Steinmetz

    IPC分类号： G06F17/50 ,  G06F9/455

    CPC分类号： G06F17/505

    摘要： Embodiments that create parent-child relationships for reuse of 1×N building blocks in a closed-loop 1×N system are disclosed. Some methods comprise generating a representation of an IC design, inserting a first 1×N building block into the representation, and creating an association between the first 1×N building block and a second 1×N building block. The association enables the first 1×N building block to inherit alterations of attributes of the second 1×N building block and enables unique alterations of attributes of the first 1×N building block which differ from the second 1×N building block. Further embodiments comprise an apparatus having an equivalency determiner to determine a logical equivalence between a two 1×N building blocks, an attribute creator that creates a set of attributes and enables one of the 1×N building blocks to inherit parent attributes and comprise child attributes.

    摘要翻译： 公开了在闭环1×N系统中创建用于重新使用1×N构建块的父子关系的实施例。 一些方法包括生成IC设计的表示，将第一个1×N构建块插入到该表示中，以及在第一个1×N构建块和第二个1×N构建块之间建立关联。 该关联使得第一个1×N构建块能够继承第二个1×N构建块的属性的改变，并且使得与第二个1×N构建块不同的第一个1×N构建块的属性的唯一改变。 另外的实施例包括具有等效确定器的装置，以确定两个1×N构建块之间的逻辑等价，创建一组属性的属性创建者，并且使得1×N构建块中的一个可以继承父属性并且包括子属性 。

    Adaptive execution cycle control method for enhanced instruction throughput
    54.
    发明授权
    Adaptive execution cycle control method for enhanced instruction throughput 失效
    用于增强指令吞吐量的自适应执行周期控制方法

    公开(公告)号：US07937568B2

    公开(公告)日：2011-05-03

    申请号：US11776121

    申请日：2007-07-11

    申请人： Anthony Correale, Jr. ,  Kenichi Tsuchiya

    发明人： Anthony Correale, Jr. ,  Kenichi Tsuchiya

    IPC分类号： G06F9/30 ,  G06F9/302

    CPC分类号： G06F1/08 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/3836 ,  G06F9/3869 ,  Y02D10/126

    摘要： A method, system and processor for increasing the instruction throughput in a processor executing longer latency instructions within the instruction pipeline. Logic associated with specific stages of the execution pipeline, responsible for executing the particular type of instructions, determines when at least a threshold number of the particular-type instructions is scheduled to be executed. The logic then automatically changes an execution cycle frequency of the specific pipeline stages from a first cycle frequency to a second, pre-established higher cycle frequency, which enables more efficient execution and higher execution throughput of the particular-type instructions. The cycle frequency of only the one or more functional stages are switched to the higher cycle frequency independent of the cycle frequency of the other functional stages in the processor pipeline. The logic also automatically switches the execution cycle frequency of the specific pipeline stages back from the second, higher cycle frequency to the first cycle frequency, when the number of scheduled first-type instructions has completed execution.

    摘要翻译： 一种用于增加处理器中的指令吞吐量的方法，系统和处理器，其执行指令流水线内的较长延迟指令。 与执行流水线的特定阶段相关联的逻辑负责执行特定类型的指令，确定何时调度执行特定类型指令的至少一个阈值数目。 逻辑然后自动地将特定流水线级的执行周期频率​​从第一周期频率改变到第二预先建立的较高周期频率，这使得能够更有效地执行特定类型指令的执行吞吐量。 只有一个或多个功能级的周期频率被切换到与处理器管线中的其他功能级的周期频率无关的较高周期频率。 当调度的第一类型指令的数量已经完成执行时，逻辑还自动将特定流水线级的执行周期频率​​从第二较高周期频率切换到第一周期频率。

    Top Level Hierarchy Wiring Via 1xN Compiler
    55.
    发明申请
    Top Level Hierarchy Wiring Via 1xN Compiler 有权
    顶级层次结构通过1xN编译器

    公开(公告)号：US20100058275A1

    公开(公告)日：2010-03-04

    申请号：US12201643

    申请日：2008-08-29

    申请人： Anthony L. Polomik ,  Benjamin J. Bowers ,  Anthony Correale, Jr. ,  Matthew W. Baker ,  Irfan Rashid ,  Paul M. Steinmetz

    发明人： Anthony L. Polomik ,  Benjamin J. Bowers ,  Anthony Correale, Jr. ,  Matthew W. Baker ,  Irfan Rashid ,  Paul M. Steinmetz

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077

    摘要： Embodiments that route 1×N building blocks using higher-level wiring information for a 1×N compiler are disclosed. Some embodiments comprise determining higher-level coordinates for a blockage of a 1×N building block, determining intra-1×N coordinates for a shape of the blockage via the higher-level coordinates, and creating routes of intra-1×N wires of the 1×N building block that avoid the intra-1×N coordinates. Further embodiments comprise an apparatus having a higher-level wiring examiner to examine higher-level wiring of an area near a 1×N building block of a physical design representation. The apparatus may also have a blockage determiner to determine a blockage that affects intra-1×N wiring for the 1×N building block and a coordinate calculator to calculate coordinates of a shape of the blockage, wherein the calculated coordinates may enable a routing tool to avoid the shape when creating intra-1×N wiring for the 1×N building block.

    摘要翻译： 公开了使用1×N编译器的更高层布线信息路由1×N构建块的实施例。 一些实施例包括确定1×N构建块的阻塞的高级坐标，通过较高级坐标确定针对阻塞形状的1×N坐标，并且创建1×N线内的1×N线 避免1×N坐标的1×N构建块。 另外的实施例包括具有更高级布线检查器以检查物理设计表示的1×N构建块附近的区域的更高级布线的装置。 该装置还可以具有阻塞确定器，以确定影响1×N构建块的1×N布线的阻塞和用于计算阻塞形状的坐标的坐标计算器，其中所计算的坐标可以使路由工具 为1×N构建块创建1×N线路时避免形状。

    Integrated Design for Manufacturing for 1xN VLSI Design
    56.
    发明申请
    Integrated Design for Manufacturing for 1xN VLSI Design 有权
    1xN VLSI设计制造综合设计

    公开(公告)号：US20100058260A1

    公开(公告)日：2010-03-04

    申请号：US12201591

    申请日：2008-08-29

    申请人： Anthony Correale, Jr. ,  Benjamin J. Bowers ,  Matthew W. Baker ,  Irfan Rashid ,  Paul M. Steinmetz

    发明人： Anthony Correale, Jr. ,  Benjamin J. Bowers ,  Matthew W. Baker ,  Irfan Rashid ,  Paul M. Steinmetz

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F2217/12

    摘要： Embodiments that make DFM alterations to cells of 1×N building blocks via a closed-loop 1×N compiler are disclosed. Some embodiments comprise using a 1×N compiler to detect a relationship between two adjacent cells of a 1×N building block. Based on the relationship, the embodiments select a DFM alteration and apply the alteration to a physical design representation. The embodiments may apply various types of DFM alterations depending on the relationship, such as adding polysilicon, adding metal to create redundant connections, and merging diffusion areas to increase capacitance on supply nodes. Further embodiments comprise an apparatus having a cell examiner to examine two adjacent cells of a 1×N building block and determine a relationship of the two cells. The apparatus also comprises a DFM selector to select a DFM alteration based on the relationship and a DFM applicator to apply the selected DFM alteration to one of the cells.

    摘要翻译： 公开了通过闭环1×N编译器使DFM改变为1×N构建块的小区的实施例。 一些实施例包括使用1×N编译器来检测1×N构建块的两个相邻小区之间的关系。 基于该关系，实施例选择DFM改变，并将改变应用于物理设计表示。 实施例可以根据关系来应用各种类型的DFM改变，例如添加多晶硅，添加金属以产生冗余连接，以及合并扩散区域以增加供应节点上的电容。 另外的实施例包括具有细胞检查器以检查1×N构建块的两个相邻小区的装置，并确定两个小区的关系。 该装置还包括一个DFM选择器，用于基于该关系选择DFM改变，并且DFM施加器将所选择的DFM改变应用于其中一个单元。

    Systems and arrangements to interconnect components of a semiconductor device
    57.
    发明授权
    Systems and arrangements to interconnect components of a semiconductor device 失效
    用于互连半导体器件的部件的系统和布置

    公开(公告)号：US07492013B2

    公开(公告)日：2009-02-17

    申请号：US11167752

    申请日：2005-06-27

    申请人： Anthony Correale, Jr.

    发明人： Anthony Correale, Jr.

    IPC分类号： H01L29/72

    CPC分类号： H01L27/0207 ,  H01L27/11807

    摘要： Systems and arrangements to interconnect cells and structures within cells of an integrated circuit to enhance cell density. Embodiments comprise an adjusted polysilicon gate pitch to metal wire pitch relationship to improve area scalars while increasing ACLV tolerance with a fixed polysilicon gate pitch. In some embodiments, the wire pitch for at least one metallization layer is adjusted to match the pitch for the polysilicon gate. In one embodiment, the next to the lowest metallization layer running in the same orientation as the polysilicon gate, utilized to access the input or output of the interconnected cell structures is relaxed to match the minimum contacted gate pitch and the metal is aligned above each polysilicon gate. In another embodiment, the polysilicon gate pitch may be relaxed to attain a smaller lowest common multiple with the wire pitch for an integrated circuit to reduce the minimum step off.

    摘要翻译： 在集成电路的单元内互连单元和结构以提高单元密度的系统和布置。 实施例包括经调整的多晶硅栅极间距与金属线间距关系，以改善面积标量，同时增加具有固定多晶硅栅极间距的ACLV容差。 在一些实施例中，调整用于至少一个金属化层的导线间距以匹配多晶硅栅极的间距。 在一个实施例中，与用于访问互连电池结构的输入或输出的用于与多晶硅栅极相同的取向运行的最低金属化层的下一个被放宽以匹配最小接触栅极间距，并且金属在每个多晶硅 门。 在另一个实施例中，多晶硅栅极间距可以被放宽以获得较小的最小公倍数，同时集成电路的导线间距可以减小最小偏移。

    Cache organization for power optimized memory access
    59.
    发明授权
    Cache organization for power optimized memory access 有权
    缓存组织，用于优化内存访问

    公开(公告)号：US07475192B2

    公开(公告)日：2009-01-06

    申请号：US11180333

    申请日：2005-07-12

    申请人： Anthony Correale, Jr. ,  Robert Lewis Goldiez

    发明人： Anthony Correale, Jr. ,  Robert Lewis Goldiez

    IPC分类号： G06F12/06

    CPC分类号： G06F12/0851 ,  G06F12/0864 ,  G06F2212/1028 ,  Y02D10/13

    摘要： An N-set associative cache organization is disclosed. The cache organization comprises a plurality of SRAMs, wherein the data within the SRAMs such that a first 1/N of a plurality of cache lines is within a first portion of the plurality of SRAMs and last 1/N portion of the plurality of cache lines is within a last portion plurality of SRAMs. By using this method for organizing the caches, power can be reduced. Given an N-way set associative cache, in this method provides up to 1/N power reduction in the data portions of the SRAMs.

    摘要翻译： 公开了一种N组关联高速缓存组织。 高速缓存组织包括多个SRAM，其中SRAM内的数据使得多个高速缓存行中的第一个1 / N在多个SRAM的第一部分内，并且多个高速缓存行中的最后1 / N部分 在多个SRAM的最后部分内。 通过使用这种组织缓存的方法，可以减少功率。 给定一个N路组相关高速缓存，在这种方法中，SRAM的数据部分提供高达1 / N的功率降低。

    Methods, systems, and media to improve manufacturability of semiconductor devices
    60.
    发明授权
    Methods, systems, and media to improve manufacturability of semiconductor devices 有权
    方法，系统和媒体，以提高半导体器件的可制造性

    公开(公告)号：US07343570B2

    公开(公告)日：2008-03-11

    申请号：US11265641

    申请日：2005-11-02

    申请人： Benjamin J. Bowers ,  Anthony Correale, Jr.

    发明人： Benjamin J. Bowers ,  Anthony Correale, Jr.

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F2217/12 ,  Y02P90/265

    摘要： Methods, systems, and media to improve the manufacturability of cells and structures within cells of an integrated circuit are disclosed. Embodiments comprise a method of arranging programmable cells, routing the programmable cells, analyzing the cell arrangement and interconnect wiring for manufacturing improvement opportunities, and modifying the programmable cell structures to incorporate the manufacturing improvements. In some embodiments, wires are spread to prevent shorting. In other embodiments, the reliability of contacts and vias is improved by adding additional metallization to the areas surrounding the contacts and vias, or by adding redundant contacts and vias. In one embodiment, a series of manufacturing improvements are made to integrated circuit cells in an iterative fashion.

    摘要翻译： 公开了用于提高集成电路单元内的单元和结构的可制造性的方法，系统和介质。 实施例包括布置可编程单元，布线可编程单元，分析单元布置并互连布线以用于制造改进机会的方法，以及修改可编程单元结构以结合制造改进。 在一些实施例中，布线以防止短路。 在其他实施例中，通过向周围的触点和通孔附加额外的金属化，或通过添加冗余的触点和通孔来改善触点和通孔的可靠性。 在一个实施例中，以迭代方式对集成电路单元进行一系列制造改进。