公开(公告)号：US20060006454A1

公开(公告)日：2006-01-12

申请号：US11120691

申请日：2005-05-02

Applicant: Chih-Hsin Wang

Inventor： Chih-Hsin Wang

IPC: H01L29/76

CPC classification number: H01L29/42324 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/792

Abstract: A nonvolatile memory cell is provided. The cell has a charge filter, a tunneling gate, a ballistic gate, a charge storage layer, a source, and a drain with a channel defined between the source and drain. The charge filter permits transporting of charge carriers of one polarity type from the tunneling gate through the blocking material and the ballistic gate to the charge storage layer while blocking the transport of charge carriers of an opposite polarity from the ballistic gate to the tunneling gate. Further embodiments of the present invention provide a cell having a charge filter, a supplier gate, a tunneling gate, a ballistic gate, a source, a drain, a channel, and a charge storage layer. The present invention further provides an energy band engineering method permitting the memory cell be operated without suffering from disturbs, from dielectric breakdown, from impact ionization, and from undesirable RC effects.

Abstract translation: 提供非易失性存储单元。 电池具有在源极和漏极之间限定的沟道的电荷滤波器，隧道栅极，弹道栅极，电荷存储层，源极和漏极。 电荷滤波器允许将一种极性类型的载流子从隧道栅极通过阻挡材料和弹道栅传输到电荷存储层，同时阻止相反极性的电荷载体从弹道栅极传输到隧道栅极。 本发明的另外的实施例提供了一种具有电荷滤波器，供电门，隧道门，弹道门，源极，漏极，沟道和电荷存储层的电池。 本发明进一步提供了允许存储器单元在不受到电介质击穿，不受冲击电离和不期望的RC影响的干扰的情况下运行的能带工程方法。

公开(公告)号：US20050169041A1

公开(公告)日：2005-08-04

申请号：US11006237

申请日：2005-04-13

Applicant: Chih-Hsin Wang

Inventor： Chih-Hsin Wang

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  G11C11/00

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7885

Abstract: A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes an electrical conductive floating gate formed in a trench in a semiconductor substrate, and an electrical conductive control gate having a portion disposed over and insulated from the floating gate. An electrical conductive tunneling gate is disposed over and insulated from the control gate by an insulating layer to form a tri-layer structure permitting both electron and hole charges tunneling through at similar tunneling rate. Spaced apart source and drain regions are formed with the source region disposed adjacent to and insulated from a lower portion of the floating gate, and with the drain region disposed adjacent to and insulated from an upper portion of the floating gate with a channel region formed therebetween and along a sidewall of the trench.

Abstract translation: 一种形成浮栅存储器单元阵列的方法，以及由此形成的阵列，其中每个存储单元包括形成在半导体衬底中的沟槽中的导电浮动栅极，以及导电控制栅极，其具有设置在绝缘上的部分 从浮动门。 导电隧道栅极通过绝缘层设置在控制栅极之上并与控制栅极绝缘，以形成三层结构，允许电子和空穴电荷以类似的隧穿速率隧穿。 间隔开的源极和漏极区域形成有源极区域，其设置为与浮置栅极的下部相邻并与其绝缘，并且漏极区域设置成与浮置栅极的上部相邻并与之隔绝，其中沟道区域形成在其间 并且沿着沟槽的侧壁。

公开(公告)号：US07745286B2

公开(公告)日：2010-06-29

申请号：US11879090

申请日：2007-07-16

Applicant: Chih-Hsin Wang

Inventor： Chih-Hsin Wang

IPC: H01L21/336

CPC classification number: H01L27/115 ,  G11C16/0416 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/7885 ,  H01L29/792

Abstract: A method of providing a memory cell comprises providing a semiconductor substrate including a body of a first conductivity type, first and second regions of a second conductivity type and a channel between the first and second regions; arranging a first insulator layer adjacent to the channel; arranging a charge storage region adjacent to the first insulator layer; arranging a second insulator layer adjacent to the charge storage region; arranging a first conductive region adjacent to the second insulator layer; arranging a filter adjacent to the first conductive region; and arranging a second conductive region adjacent to the filter. The second conductive region overlaps the first conductive region at an overlap surface. A line perpendicular to the overlap surface intersects at least a portion of the charge storage region.

Abstract translation: 提供存储单元的方法包括：提供包括第一导电类型的主体，第二导​​电类型的第一和第二区域以及第一和第二区域之间的通道的半导体衬底; 布置与所述通道相邻的第一绝缘体层; 配置与所述第一绝缘体层相邻的电荷存储区域; 布置与电荷存储区域相邻的第二绝缘体层; 布置与所述第二绝缘体层相邻的第一导电区域; 布置与所述第一导电区域相邻的过滤器; 以及布置与所述过滤器相邻的第二导电区域。 第二导电区域在重叠表面处与第一导电区域重叠。 垂直于重叠表面的线与电荷存储区域的至少一部分相交。

公开(公告)号：US07719050B1

公开(公告)日：2010-05-18

申请号：US12157380

申请日：2008-06-10

Applicant: Chih-Hsin Wang

Inventor： Chih-Hsin Wang

IPC: H01L29/06 ,  H01L29/76 ,  H01L21/336

CPC classification number: H01L27/115 ,  G11C16/0466 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42336 ,  H01L29/47 ,  H01L29/66825

Abstract: A memory cell comprises a body of a semiconductor material having a first conductivity type. A conductor-filter system includes a first conductor having thermal charge carriers, and a filter contacting the first conductor and including dielectrics for providing a filtering function on the charge carriers of one polarity. The filter includes a first set of electrically alterable potential barriers. A conductor-insulator system includes a second conductor and a first insulator contacting the second conductor at an interface and having a second set of electrically alterable potential barriers. A first region is spaced-apart from the second conductor. A channel of the body is defined therebetween. A second insulator is adjacent to the first region. A charge storage region is disposed in between the first and the second insulators. A word-line has a first portion and a second portion comprising the first conductor disposed over and insulated from the body.

Abstract translation: 存储单元包括具有第一导电类型的半导体材料的主体。 导体滤波器系统包括具有热电荷载流子的第一导体和接触第一导体的滤波器，并且包括用于在一个极性的载流子上提供滤波功能的电介质。 过滤器包括第一组电可更改的势垒。 导体 - 绝缘体系统包括第二导体和在界面处接触第二导体的第一绝缘体，并且具有第二组电可更改的势垒。 第一区域与第二导体间隔开。 身体的通道被限定在其间。 第二绝缘体与第一区域相邻。 电荷存储区域设置在第一和第二绝缘体之间。 字线具有第一部分和第二部分，其包括设置在身体上并与身体绝缘的第一导体。

公开(公告)号：US07626864B2

公开(公告)日：2009-12-01

申请号：US11380418

申请日：2006-04-26

Applicant: Chih-Hsin Wang

Inventor： Chih-Hsin Wang

IPC: G11C11/34 ,  H01L29/788

CPC classification number: H01L29/7885 ,  G11C16/0416 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/42324

Abstract: Nonvolatile memory cells and array are provided. The memory cell comprises a body, a source, a drain, and a charge storage region. The body comprises an n-type conductivity and is formed in a well of the n-type conductivity. The source and the drain have p-type conductivity and are formed in the well with a channel of the body defined therebetween. The charge storage region is disposed over and insulated from the channel by a channel insulator. Each cell further comprises a bias setting having a source voltage applied to the source, a well voltage applied to the well, and a drain voltage applied to the drain. A bias configuration for an erase operation of the memory cell is further provided, wherein the source voltage is sufficiently more negative with respect to the well voltage and is sufficiently more positive with respect to the drain voltage to inject hot holes onto the charge storage region. The cells can be arranged in row and column to form memory arrays and memory device.

Abstract translation: 提供了非易失性存储单元和阵列。 存储单元包括主体，源极，漏极和电荷存储区域。 该主体包括n型导电性并形成在n型导电性的阱中。 源极和漏极具有p型导电性，并且在阱中形成有在其间限定的主体的沟道。 电荷存储区域通过沟道绝缘体设置在通道上并与通道绝缘。 每个单元还包括具有施加到源极的源极电压，施加到阱的阱电压和施加到漏极的漏极电压的偏置设置。 还提供了用于存储单元的擦除操作的偏置配置，其中源极电压相对于阱电压足够多地为负，并且相对于漏极电压而言足够地为正向，以将热空穴注入电荷存储区域。 单元格可以以行和列排列以形成存储器阵列和存储器件。

公开(公告)号：US07595728B2

公开(公告)日：2009-09-29

申请号：US11356584

申请日：2006-02-17

Applicant: Chih-Hsin Wang

Inventor： Chih-Hsin Wang

IPC: G08B13/14

CPC classification number: G08B13/2445

Abstract: A system for tracking elements employing fixed tags that are permanently attached to elements. The tags include radio-frequency (RF) communication units that are adapted for wireless communication with RF communicators. The RF tags are permanently affixed to elements as part of the manufacturing of products such as cell phones, PDA's, computers, routers and other electronic equipment. The RF tags are installed during manufacturing in a manner that resists tampering and interference. The RF tags are installed with mechanical barriers to access and are hidden from view in non-user accessible locations.

Abstract translation: 用于跟踪元件的系统，该元件使用固定的标签永久地附接到元件。 标签包括适于与RF通信器的无线通信的射频（RF）通信单元。 作为制造诸如手机，PDA，计算机，路由器和其他电子设备的产品的一部分，RF标签永久地附着在元件上。 RF标签在制造过程中以防止篡改和干扰的方式安装。 RF标签安装有访问的机械屏障，并在非用户可访问的位置隐藏。

公开(公告)号：US07550800B2

公开(公告)日：2009-06-23

申请号：US11169399

申请日：2005-06-28

Applicant: Chih-Hsin Wang

Inventor： Chih-Hsin Wang

IPC: H01L21/336 ,  H01L21/331

CPC classification number: H01L27/115 ,  G11C16/0416 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/7885 ,  H01L29/792

Abstract: A conductor-filter system, a conductor-insulator system, and a charge-injection system are provided. The conductor-filter system provides band-pass filtering function, charge-filtering function, voltage-divider function, and mass-filtering function to charge-carriers flows. The conductor-insulator system provides Image-Force barrier lowering effect to collect charge-carriers. The charge-injection system includes the conductor-filter system and the conductor-insulator system, wherein the filter of the conductor-filter system contacts the conductor of the conductor-insulator system. Method and apparatus on charges filtering, injection, and collection are provided for semiconductor device and nonvolatile memory device. Additionally, method and apparatus on charges injection using piezo-ballistic-charges injection mechanism are provided to the charge-injection system and devices operation. Memory cells and array architectures and manufacturing method thereof are provided.

Abstract translation: 提供导体滤波器系统，导体 - 绝缘体系统和电荷注入系统。 导体滤波器系统为电荷载流子提供带通滤波功能，电荷滤波功能，分压功能和质量滤波功能。 导体 - 绝缘体系统提供图像强制屏障降低效应以收集电荷载体。 电荷注入系统包括导体 - 滤波器系统和导体 - 绝缘体系统，其中导体 - 滤波器系统的滤波器接触导体 - 绝缘体系统的导体。 为半导体器件和非易失性存储器件提供电荷过滤，注入和收集的方法和装置。 另外，在电荷注入系统和装置的操作中提供了使用压电弹药注入机构的电荷注入的方法和装置。 提供了存储单元和阵列结构及其制造方法。

公开(公告)号：US07372734B2

公开(公告)日：2008-05-13

申请号：US11346816

申请日：2006-02-03

Applicant: Chih-Hsin Wang

Inventor： Chih-Hsin Wang

IPC: G11C11/34

CPC classification number: G11C16/14 ,  G11C16/0416 ,  H01L29/42332 ,  H01L29/7885 ,  H01L29/792

Abstract: A nonvolatile memory cell is provided. The memory cell includes a storage transistor and an injector in a well of an n-type conductivity. The well is formed in a semiconductor substrate of a p-type conductivity. The storage transistor comprises a source, a drain, a channel, and a charge storage region. The source and the drain are formed in the well and having the p-type conductivity with the channel of the well defined therebetween. The charge storage region is disposed over and insulated from the channel region by an insulator. Further provided are methods operating the memory cell, including means for injecting electrons from the channel through the insulator onto the charge storage region and means for injecting holes from the injector through the well through the channel through the insulator onto the charge storage region. The memory cell can be implemented in a conventional logic CMOS process.

Abstract translation: 提供非易失性存储单元。 存储单元包括n型导电性阱中的存储晶体管和注入器。 该阱形成在p型导电性的半导体衬底中。 存储晶体管包括源极，漏极，沟道和电荷存储区域。 源极和漏极形成在阱中并且具有p型导电性，阱之间的沟道被限定。 电荷存储区域通过绝缘体设置在沟道区域的上方并与绝缘体绝缘。 还提供了操作存储单元的方法，包括用于将电子从通道中通过绝缘体注入到电荷存储区域上的装置，以及用于将来自注射器的孔穿过阱通过穿过绝缘体的沟槽注入到电荷存储区上的装置。 存储器单元可以在传统的逻辑CMOS工艺中实现。

公开(公告)号：US20070281426A1

公开(公告)日：2007-12-06

申请号：US11879179

申请日：2007-07-16

Applicant: Chih-Hsin Wang

Inventor： Chih-Hsin Wang

IPC: H01L21/336

CPC classification number: H01L27/115 ,  G11C16/0416 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/7885 ,  H01L29/792

Abstract: A method of providing a memory cell comprises providing a semiconductor substrate including a body of a first conductivity type, first and second regions of a second conductivity type and a channel between the first and second regions; arranging a first insulator layer adjacent to the substrate; arranging a charge storage region adjacent to the first insulator layer; arranging a second insulator layer adjacent to the charge storage region; arranging a first conductive region adjacent to the second insulator layer; arranging a layer adjacent to the first conductive region; arranging a second conductive region adjacent to the layer; and increasing mechanical stress of at least one of the first and second conductive regions. The second conductive region overlaps the first conductive region at an overlap surface, and wherein a line perpendicular to the overlap surface intersects at least a portion of the charge storage region

Abstract translation: 提供存储单元的方法包括：提供包括第一导电类型的主体，第二导​​电类型的第一和第二区域以及第一和第二区域之间的通道的半导体衬底; 布置与所述基板相邻的第一绝缘体层; 配置与所述第一绝缘体层相邻的电荷存储区域; 布置与电荷存储区域相邻的第二绝缘体层; 布置与所述第二绝缘体层相邻的第一导电区域; 布置与所述第一导电区域相邻的层; 布置与所述层相邻的第二导电区域; 以及增加所述第一和第二导电区域中的至少一个的机械应力。 第二导电区域在重叠表面处与第一导电区域重叠，并且其中垂直于重叠表面的线与电荷存储区域的至少一部分相交，

公开(公告)号：US07297634B2

公开(公告)日：2007-11-20

申请号：US11055427

申请日：2005-02-09

Applicant: Chih-Hsin Wang

Inventor： Chih-Hsin Wang

IPC: H01L21/311

CPC classification number: H01L27/115 ,  G11C16/0416 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/42336 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/7885 ,  H01L29/792

Abstract: Method and apparatus on charges injection using piezo-ballistic-charges injection mechanism are provided for semiconductor device and nonvolatile memory device. The device comprises a strain source, an injection filter, a first conductive region, a second conductive region, and a charge collecting region. The strain source permits piezo-effect in ballistic charges transport to enable the piezo-ballistic-charges injection mechanism in device operations. The injection filter permits transporting of charge carriers of one polarity type from the first conductive region, through the filter, and through the second conductive region to the charge collecting region while blocking the transport of charge carriers of an opposite polarity from the second conductive region to the first conductive region. The present invention further provides an energy band engineering method permitting the devices be operated without suffering from disturbs, from dielectric breakdown, from impact ionization, and from undesirable RC effects.

Abstract translation: 为半导体器件和非易失性存储器件提供使用压电弹注电荷注入机构的电荷注入的方法和装置。 该装置包括应变源，注射过滤器，第一导电区域，第二导电区域和电荷收集区域。 应变源允许在弹道电荷输送中的压电效应，使得能够在器件操作中实现压电弹药注入机制。 注入过滤器允许将一种极性类型的电荷载体从第一导电区域，过滤器和第二导电区域传送到电荷收集区域，同时阻止相反极性的电荷载体从第二导电区域传输到 第一导电区域。 本发明进一步提供一种能量带工程方法，其允许在不受到电介质击穿，不受冲击电离和不期望的RC影响的干扰的情况下操作装置。