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438 条记录 (耗时 0.066 秒)

    Handling processor computational errors
    53.
    发明授权
    Handling processor computational errors 失效
    处理处理器计算错误

    公开(公告)号：US08375247B2

    公开(公告)日：2013-02-12

    申请号：US11364131

    申请日：2006-02-28

    申请人： Bran Ferren ,  W. Daniel Hillis ,  William Henry Mangione-Smith ,  Nathan P. Myhrvold ,  Clarence T. Tegreene ,  Lowell L. Wood, Jr.

    发明人： Bran Ferren ,  W. Daniel Hillis ,  William Henry Mangione-Smith ,  Nathan P. Myhrvold ,  Clarence T. Tegreene ,  Lowell L. Wood, Jr.

    IPC分类号： G06F11/00

    CPC分类号： G06F11/0793 ,  G06F11/0721 ,  G06F11/1407

    摘要： Embodiments include a computer processor-error controller, a computerized device, a device, an apparatus, and a method. A computer processor-error controller includes a monitoring circuit operable to detect a computational error corresponding to an execution of a second instruction by a processor operable to execute a sequence of program instructions that includes a first instruction that is fetched before the second instruction. The computer processor-error controller includes an error recovery circuit operable to restore an execution of the sequence of program instructions to the first instruction in response to the detected computational error.

    摘要翻译： 实施例包括计算机处理器 - 错误控制器，计算机化设备，设备，设备和方法。 计算机处理器错误控制器包括监视电路，其可操作以由处理器检测对应于执行第二指令的计算错误，所述处理器可操作以执行包括在所述第二指令之前获取的第一指令的程序指令序列。 计算机处理器错误控制器包括错误恢复电路，其可操作以响应于检测到的计算错误将程序指令序列的执行恢复到第一指令。

    Hardware-error tolerant computing
    54.
    发明授权
    Hardware-error tolerant computing 有权
    硬件容错计算

    公开(公告)号：US08255745B2

    公开(公告)日：2012-08-28

    申请号：US12319696

    申请日：2009-01-08

    申请人： Bran Ferren ,  W. Daniel Hillis ,  William Henry Mangione-Smith ,  Nathan P. Myhrvold ,  Clarence T Tegreene ,  Lowell L. Wood, Jr.

    发明人： Bran Ferren ,  W. Daniel Hillis ,  William Henry Mangione-Smith ,  Nathan P. Myhrvold ,  Clarence T Tegreene ,  Lowell L. Wood, Jr.

    IPC分类号： G06F11/00

    CPC分类号： G06F11/0793 ,  G06F11/0721 ,  G06F11/1407

    摘要： Embodiments include a computing system, a device, and a method. A computing system includes a processor subsystem having an adjustable operating parameter. The computing system also includes an information store operable to save a sequence of instructions. The computing system further includes a controller module. The controller module includes a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem. The controller further includes a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion.

    摘要翻译： 实施例包括计算系统，设备和方法。 计算系统包括具有可调操作参数的处理器子系统。 计算系统还包括可操作以保存指令序列的信息存储器。 计算系统还包括控制器模块。 控制器模块包括监视器电路，用于检测由处理器子系统执行指令序列的指令所对应的操作参数引起的错误的入射。 控制器还包括一个控制电路，用于根据容错性能标准来调节可调节的操作参数。

    Processor resource management
    56.
    发明申请
    Processor resource management 有权
    处理器资源管理

    公开(公告)号：US20090327671A1

    公开(公告)日：2009-12-31

    申请号：US12454633

    申请日：2009-05-19

    申请人： Bran Ferren ,  W. Daniel Hillis ,  Nathan P. Myhrvold ,  Clarence T. Tegreene ,  Lowell L. Wood, JR.

    发明人： Bran Ferren ,  W. Daniel Hillis ,  Nathan P. Myhrvold ,  Clarence T. Tegreene ,  Lowell L. Wood, JR.

    IPC分类号： G06F9/00 ,  G06F9/30

    CPC分类号： G06F12/0862 ,  G06F9/5016 ,  G06F11/008 ,  G06F2212/6028

    摘要： Processor resource management devices and methods are disclosed. In some implementations, a device includes a processor, a hardware resource, and a resource manager operable to compare a first execution of one or more instructions pursuant to an optimistic resource management policy and a second execution of one or more instructions pursuant to a pessimistic resource management policy, the optimistic resource management policy assuming that less than an optimistic level of at least one error will occur during the first execution, and the pessimistic resource management policy assuming that greater than a pessimistic level of the at least one error will occur during the second execution. Based at least partially on the comparison, the resource manager selects a resource management policy from between the optimistic and pessimistic resource management policies, and associates the selected resource management policy with the one or more instructions.

    摘要翻译： 公开了处理器资源管理设备和方法。 在一些实现中，设备包括处理器，硬件资源和资源管理器，其可操作以根据乐观的资源管理策略和根据悲观资源的一个或多个指令的第二执行来比较一个或多个指令的第一执行 管理政策，乐观的资源管理政策假设在第一次执行期间将发生少于至少一个错误的乐观水平，而悲观的资源管理策略假定在该期间将发生大于至少一个错误的悲观程度 第二次执行。 至少部分地基于比较，资源管理器从乐观和悲观的资源管理策略之间选择资源管理策略，并且将所选择的资源管理策略与一个或多个指令相关联。