公开(公告)号：US06570433B2

公开(公告)日：2003-05-27

申请号：US09925918

申请日：2001-08-09

申请人： Anthony Gus Aipperspach ,  Todd Alan Christensen

发明人： Anthony Gus Aipperspach ,  Todd Alan Christensen

IPC分类号： H01H8500

CPC分类号： H01L23/5258 ,  H01L27/0255 ,  H01L27/1203 ,  H01L2924/0002 ,  H03K17/08122 ,  H03K17/08142 ,  H01L2924/00

摘要： A method and apparatus are provided for laser fuseblow protection in transistors, such as silicon-on-insulator (SOI) transistors. The transistors are connected to a fuse. A pair of diodes are connected in series between a high supply and ground. A common connection of the series connected pair of diodes is connected to a common connection of the fuse and transistors. A charge is shunted to the high supply or ground by the pair of diodes with a first voltage a set value above the high supply and a second voltage a set value below the ground. A pair of protection diodes are provided on each side of the fuse with transistors. The transistors are either connected to one side of the fuse or to both sides of the fuse.

公开(公告)号：US06404686B1

公开(公告)日：2002-06-11

申请号：US09770912

申请日：2001-01-26

申请人： Anthony Gus Aipperspach ,  Fariborz Assaderaghi ,  Todd Alan Christensen ,  Douglas Michael Dewanz ,  Jente Benedict Kuang

发明人： Anthony Gus Aipperspach ,  Fariborz Assaderaghi ,  Todd Alan Christensen ,  Douglas Michael Dewanz ,  Jente Benedict Kuang

IPC分类号： G11C700

CPC分类号： G11C7/065

摘要： A high performance, low cell stress, low-power silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) latch-type sensing method and apparatus are provided. A silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) latch-type sense amplifier includes a precharge circuit for charging complementary bit and data lines to a predefined precharge voltage during a precharge cycle. The precharge voltage is lower than a full rail voltage. The reduced bit and data line precharge voltage substantially reduces voltage stress applied to the access transistors in the RAM cells. A pre-amplifying mechanism produces an offset voltage between the complementary data lines before the. sense amplifier is set. The pre-amplifying mechanism includes a pre-amplifying FET that is substantially smaller than a sensing silicon-on-insulator (SOI) field effect transistor (FET) in the sense amplifier. The pre-amplifying mechanism aids offset voltage development before the sense amplifier is set. The full rail voltage is provided for the complementary data lines when the sense amplifier is set. The full rail voltage can be applied during the write mode.

摘要翻译： 提供了高性能，低电池应力，低功率绝缘体上硅（SOI）互补金属氧化物半导体（CMOS）闩锁型感测方法和装置。 绝缘体上硅（SOI）互补金属氧化物半导体（CMOS）锁存型读出放大器包括预充电电路，用于在预充电循环期间将互补位和数据线充电至预定的预充电电压。 预充电电压低于全路电压。 减小的位和数据线预充电电压基本上减小施加到RAM单元中的存取晶体管的电压。 预放大机制在之前的互补数据线之间产生偏移电压。 读出放大器设置。 该预放大机构包括一个预放大FET，该预放大FET基本上小于感测放大器中的感测绝缘体上（SOI）场效应晶体管（FET）。 预放大机制有助于在读出放大器设置之前的偏移电压发展。 当设置读出放大器时，为互补数据线提供全路电压。 在写入模式期间可以应用全路电压。

公开(公告)号：US06275427B1

公开(公告)日：2001-08-14

申请号：US09552119

申请日：2000-04-19

申请人： Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Douglas Michael Dewanz

发明人： Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Douglas Michael Dewanz

IPC分类号： G11C700

CPC分类号： G11C29/50 ,  G11C11/41

摘要： An apparatus, program product, and method of testing a silicon-on-insulator (SOI) static random access memory (SRAM) introduce switching history effects to a memory cell under test to stress the memory cell such that a reliable determination of stability may be made. It has been found that the worst case scenario for memory cell stability typically occurs immediately after a memory cell is switched to one state after the memory cell has been maintained in the other, opposite state for a period of time sufficient to introduce switching history effects. As such, a testing process may be configured to maintain a memory cell in a particular state for a period of time sufficient to introduce switching history effects, whereby the memory cell may be adequately stressed during the testing process to highlight any stability problems by setting the memory cell to an opposite state, and then shortly thereafter disturbing the memory cell, e.g., via a read to the memory cell or another memory cell on the same column or row of a memory array.

摘要翻译： 一种测试绝缘体上硅（SOI）静态随机存取存储器（SRAM）的装置，程序产品和方法将切换历史效应引入到被测存储单元，以对存储单元施加压力，从而可靠地确定稳定性 制作。 已经发现，在存储器单元已经被保持在另一个相反状态一段时间之后，存储器单元切换到一个状态之后，存储单元稳定性的最坏情况通常发生在足以引入切换历史效应的时间段内。 因此，测试过程可以被配置为将存储器单元维持在特定状态一段足以引入切换历史效应的时间段，由此在测试过程中存储器单元可以被充分地应力以突出任何稳定性问题，通过设置 存储器单元处于相反状态，然后不久以后干扰存储器单元，例如，通过读取到存储器单元或存储器阵列的相同列或行上的另一个存储器单元。

公开(公告)号：US06172531B2

公开(公告)日：2001-01-09

申请号：US09251089

申请日：1999-02-16

申请人： Anthony Gus Aipperspach ,  Peter Thomas Freiburger

发明人： Anthony Gus Aipperspach ,  Peter Thomas Freiburger

IPC分类号： H03K190948

CPC分类号： G11C8/10 ,  G11C8/08 ,  H03K19/0963

摘要： A wordline decoder circuit and method of decoding a wordline input signal are provided. A first decoder receives multiple inputs to be evaluated. The first decoder includes a first precharge device for precharging a first node and a first discharge device to enable discharging the first node. A first clock signal enables the first discharge device. The first clock signal disables the precharge device. A clock delay circuit receives the first clock signal and generates a delayed clock signal. A second logic is coupled to the first decoder. The second logic provides a wordline output. The second logic wordline output is enabled responsive to the delayed clock signal and is disabled responsive to the first clock signal.

摘要翻译： 提供了字线解码器电路和对字线输入信号进行解码的方法。 第一解码器接收要评估的多个输入。 第一解码器包括用于对第一节点进行预充电的第一预充电装置和用于使第一节点放电的第一放电装置。 第一时钟信号使能第一放电装置。 第一个时钟信号禁止预充电设备。 时钟延迟电路接收第一时钟信号并产生延迟的时钟信号。 第二逻辑耦合到第一解码器。 第二个逻辑提供字线输出。 第二逻辑字线输出响应于延迟的时钟信号被使能，并且响应于第一时钟信号被禁止。

公开(公告)号：US5991208A

公开(公告)日：1999-11-23

申请号：US084134

申请日：1998-05-22

申请人： Anthony Gus Aipperspach ,  Peter Thomas Freiburger ,  Peder James Paulson

发明人： Anthony Gus Aipperspach ,  Peter Thomas Freiburger ,  Peder James Paulson

IPC分类号： G11C8/16 ,  G11C7/00

CPC分类号： G11C8/16

摘要： An improved apparatus and method for facilitating multiple write port access to a programmable memory apparatus is disclosed. A memory array, such as a random access memory array, includes a plurality of memory cells. A number of write ports are coupled to the memory array, each of which provides write access to individual memory cells of the memory array. Each of the write ports includes a NAND gate, an inverter, and a transfer gate. The NAND gate includes first and second inputs respectively coupled to a write row select line and a write column select line, and an output coupled to the input of the inverter and a first control input of the transfer gate. The output of the inverter is coupled to a second control input of the transfer gate. The input of the transfer gate is coupled to a data line, and the output of the transfer gate is coupled to a memory cell of the memory array. In response to appropriate logic levels on the write row select line and write column select line, data on the data input line is transferred through the transfer gate and written into the memory cell. Reduced node capacitance at the input of the memory cell and an increase in memory cell write speed are realized by implementing the disclosed write port circuitry.

摘要翻译： 公开了一种用于促进对可编程存储装置的多个写入口访问的改进的装置和方法。 诸如随机存取存储器阵列的存储器阵列包括多个存储器单元。 多个写入端口耦合到存储器阵列，每个写入端口提供对存储器阵列的各个存储器单元的写访问。 每个写入端口包括NAND门，反相器和传输门。 NAND门包括分别耦合到写入行选择线和写入列选择线的第一和第二输入，以及耦合到反相器的输入和传输门的第一控制输入的输出。 反相器的输出耦合到传输门的第二控制输入端。 传输门的输入耦合到数据线，并且传输门的输出耦合到存储器阵列的存储单元。 响应于写行选择线和写列选择线上的适当逻辑电平，数据输入线上的数据通过传输门传输并写入存储单元。 通过实现所公开的写入端口电路来实现在存储器单元输入端减少的节点电容和存储单元写入速度的增加。