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    Layout to minimize FET variation in small dimension photolithography
    1.
    发明授权
    Layout to minimize FET variation in small dimension photolithography 有权
    布局以最小化小尺度光刻中的FET变化

    公开(公告)号：US08860141B2

    公开(公告)日：2014-10-14

    申请号：US13345439

    申请日：2012-01-06

    申请人： Derick Gardner Behrends ,  Todd Alan Christensen ,  Travis Reynold Hebig ,  Michael Launsbach ,  Daniel Mark Nelson

    发明人： Derick Gardner Behrends ,  Todd Alan Christensen ,  Travis Reynold Hebig ,  Michael Launsbach ,  Daniel Mark Nelson

    IPC分类号： H01L21/70

    CPC分类号： H01L27/1104 ,  G11C5/025 ,  H01L21/28123 ,  H01L27/0207

    摘要： A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during processing. A circuit on the semiconductor chip requires close tracking between a first and a second FET (field effect transistor). For example, the particular level may be a gate shape level. Separate exposures of gate shapes using the first mask and the second mask will result in poorer FET tracking (e.g., gate length, threshold voltage) than for FETs having gate shapes defined by only the first mask. FET tracking is selectively improved by laying out a circuit such that selective FETs are defined by the first mask. In particular, static random access memory (SRAM) design benefits from close tracking of six or more FETs in an SRAM cell.

    摘要翻译： 半导体芯片具有在足够小以至要求第一掩模和第二掩模的特定等级上的形状，第一掩模和第二掩模在处理期间分开曝光中使用。 半导体芯片上的电路需要在第一和第二FET（场效应晶体管）之间的紧密跟踪。 例如，特定级别可以是门形状级别。 使用第一掩模和第二掩模的栅极形状的单独曝光将导致比仅由第一掩模限定的栅极形状的FET更差的FET跟踪（例如，栅极长度，阈值电压）。 通过布置电路来选择性地提高FET跟踪，使得选择性FET由第一掩模限定。 特别地，静态随机存取存储器（SRAM）设计受益于在SRAM单元中紧密跟踪六个或更多个FET。

    DATA SECURITY FOR DYNAMIC RANDOM ACCESS MEMORY USING BODY BIAS TO CLEAR DATA AT POWER-UP
    3.
    发明申请
    DATA SECURITY FOR DYNAMIC RANDOM ACCESS MEMORY USING BODY BIAS TO CLEAR DATA AT POWER-UP 有权
    动态随机存取存储器的数据安全使用身体偏差清除数据上电

    公开(公告)号：US20120087176A1

    公开(公告)日：2012-04-12

    申请号：US12898924

    申请日：2010-10-06

    申请人： Derick Gardner Behrends ,  Todd Alan Christensen ,  Travis Reynold Hebig ,  Michael Launsbach ,  Daniel Mark Nelson

    发明人： Derick Gardner Behrends ,  Todd Alan Christensen ,  Travis Reynold Hebig ,  Michael Launsbach ,  Daniel Mark Nelson

    IPC分类号： G11C11/24 ,  G11C7/00

    CPC分类号： G11C7/24 ,  G11C5/145 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4078

    摘要： A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by increasing the body voltage of cells. In the example circuit, the body voltage is increased by a charge pump controlled by a power-on-reset (POR) signal applying a voltage to the p-well of the memory cells. The added voltage to the p-well lowers the threshold voltage of the cell, such that the NFET transistor of the memory cell will turn on. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value.

    摘要翻译： 电路和方法在上电时擦除存储在DRAM芯片中的所有数据，以提高数据安全性。 通过增加单元的体电压同时接通DRAM存储单元的晶体管，可以擦除所有的DRAM存储单元。 在示例电路中，通过由对存储器单元的p阱施加电压的上电复位（POR）信号控制的电荷泵增加体电压。 向p阱施加的电压降低了电池的阈值电压，使得存储器单元的NFET晶体管将导通。 当所有设备都打开时，存储在存储单元中的数据将被擦除，因为连接到通用位线的所有单元的电压合并为单个值。

    Implementing local evaluation of domino read SRAM with enhanced SRAM cell stability with minimized area usage
    5.
    发明授权
    Implementing local evaluation of domino read SRAM with enhanced SRAM cell stability with minimized area usage 失效
    实现对多米诺骨牌SRAM的局部评估，具有增强的SRAM单元稳定性，同时最小化区域使用率

    公开(公告)号：US07724586B2

    公开(公告)日：2010-05-25

    申请号：US12195151

    申请日：2008-08-20

    申请人： Chad Allen Adams ,  Todd Alan Christensen ,  Peter Thomas Freiburger ,  Daniel Mark Nelson

    发明人： Chad Allen Adams ,  Todd Alan Christensen ,  Peter Thomas Freiburger ,  Daniel Mark Nelson

    IPC分类号： G11C7/06 ,  G06F17/50

    CPC分类号： G11C11/413

    摘要： A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true and complement bitlines, true and complement write data propagation inputs, a precharge signal, and a precharge write signal. A respective precharge device is connected between a voltage supply VDD and the true bitline and the complement bitline. A first passgate device is connected between the complement bitline and the true write data propagation input. A second passgate device is connected between the true bitline and the complement write data propagation input. The precharge write signal disables the passgate devices during a read operation. During write operations, the precharge write signal enables the passgate devices.

    摘要翻译： 一种用于实现具有增强的SRAM单元稳定性的多米诺骨牌静态随机存取存储器（SRAM）局部评估的方法和电路，以及提供主题电路所在的设计结构。 实现相关SRAM单元组的读和写操作的SRAM本地评估电路包括真和补补位线，真和补写写数据传播输入，预充电信号和预充电写信号。 相应的预充电装置连接在电压源VDD与真位线和补码位线之间。 第一传递门装置连接在补码位线和真实写入数据传播输入端之间。 第二个通路装置连接在真位线和补码写入数据传播输入之间。 在读取操作期间，预充电写信号禁用通路器件。 在写入操作期间，预充电写入信号使能通路装置。

    Implementing Decoupling Capacitors With Hot-Spot Thermal Reduction on Integrated Circuit Chips
    6.
    发明申请
    Implementing Decoupling Capacitors With Hot-Spot Thermal Reduction on Integrated Circuit Chips 失效
    在集成电路芯片上实现热点热还原实现去耦电容

    公开(公告)号：US20100032799A1

    公开(公告)日：2010-02-11

    申请号：US12186837

    申请日：2008-08-06

    申请人： Gerald Keith Bartley ,  Todd Alan Christensen ,  Paul Eric Dahlen ,  John Edward Sheets, II

    发明人： Gerald Keith Bartley ,  Todd Alan Christensen ,  Paul Eric Dahlen ,  John Edward Sheets, II

    IPC分类号： H01L29/00 ,  H01L21/20

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/0805

    摘要： A method and structures are provided for implementing decoupling capacitors with hot spot thermal reduction on integrated circuit chips including silicon-on-insulator (SOI) circuits. A silicon-on-insulator (SOI) structure includes a silicon substrate layer, a thin buried oxide (BOX) layer carried by the silicon substrate layer, and an active layer carried by the thin BOX layer. A thermal conductive path is built proximate to a hotspot area in the active layer to reduce thermal effects including a backside thermal connection from a backside of the SOI structure. The backside thermal connection includes a backside etched opening extending from the backside of the SOI structure into the silicon substrate layer, a capacitor dielectric formed on said backside etched opening; and a thermal connection material deposited on said capacitor dielectric filling said backside etched opening.

    摘要翻译： 提供了一种方法和结构，用于在包括绝缘体上硅（SOI）电路的集成电路芯片上实现具有热点热还原的去耦电容器。 绝缘体上硅（SOI）结构包括硅衬底层，由硅衬底层承载的薄掩埋氧化物（BOX）层以及由薄BOX层承载的有源层。 在有源层中的热点区域附近建立导热路径，以减少热效应，包括来自SOI结构背面的背面热连接。 背面热连接包括从SOI结构的背面延伸到硅衬底层的后侧蚀刻开口，形成在所述背面蚀刻开口上的电容器电介质; 以及沉积在填充所述背面蚀刻开口的所述电容器电介质上的热连接材料。

    Method and circuit for implementing enhanced LBIST testing of paths including arrays
    7.
    发明申请
    Method and circuit for implementing enhanced LBIST testing of paths including arrays 有权
    用于实现包括阵列的路径的增强型LBIST测试的方法和电路

    公开(公告)号：US20090183044A1

    公开(公告)日：2009-07-16

    申请号：US12015254

    申请日：2008-01-16

    申请人： Louis Bernard Bushard ,  Todd Alan Christensen ,  Jesse Daniel Smith

    发明人： Louis Bernard Bushard ,  Todd Alan Christensen ,  Jesse Daniel Smith

    IPC分类号： G01R31/3187 ,  G06F11/27

    CPC分类号： G01R31/3187

    摘要： A method and circuit implement testing of a circuit path including a memory array and logic including Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. Testing of the circuit path includes initializing the memory array in the circuit path with an initialization pattern, switching to Logic Built in Self Test (LBIST) mode and providing a read only mode for the memory array, and running Logic Built in Self Test (LBIST) testing of the circuit path.

    摘要翻译： 一种包括存储器阵列和逻辑的电路路径的方法和电路实现测试，包括逻辑内置自测（LBIST）诊断，以及提供了主题电路所在的设计结构。 电路路径的测试包括用初始化模式初始化电路路径中的存储器阵列，切换到逻辑内置自测（LBIST）模式，并为存储器阵列提供只读模式，并运行逻辑内置自检（LBIST） ）测试电路路径。

    Method for Implementing Level Shifter Circuits and Low Power Level Shifter Circuits for Integrated Circuits
    8.
    发明申请
    Method for Implementing Level Shifter Circuits and Low Power Level Shifter Circuits for Integrated Circuits 失效
    实现电平移位器电路的方法和用于集成电路的低功率电平移位器电路

    公开(公告)号：US20080084237A1

    公开(公告)日：2008-04-10

    申请号：US11538967

    申请日：2006-10-05

    申请人： Derick Gardner Behrends ,  Todd Alan Christensen ,  Travis Reynold Hebig

    发明人： Derick Gardner Behrends ,  Todd Alan Christensen ,  Travis Reynold Hebig

    IPC分类号： H03L5/00

    CPC分类号： H03K19/094 ,  H03K19/018521

    摘要： A low power level shifter circuit includes an input inverter operating in a domain of a first voltage supply. The input inverter receives an input signal and provides a first inverted signal. An output inverter operating in a domain of a second voltage supply coupled to the input inverter and provides an output signal having a voltage level corresponding to the second voltage supply and a logic value corresponding to the input signal. The second voltage supply is higher than the first voltage supply. A leakage current control circuit includes a finisher transistor connected between the second voltage supply and the input to the output inverter and a path control transistor control a path between the first voltage supply and the input inverter.

    摘要翻译： 低功率电平移位器电路包括在第一电压源的域中操作的输入反相器。 输入反相器接收输入信号并提供第一反相信号。 输出反相器，其在与输入反相器耦合的第二电压源的区域中工作，并提供具有与第二电压源相对应的电压电平的输出信号和对应于输入信号的逻辑值。 第二电压源高于第一电压源。 泄漏电流控制电路包括连接在第二电压源和输出反相器的输入端之间的整流晶体管，并且路径控制晶体管控制第一电压源与输入反相器之间的路径。

    Split local and continuous bitline for fast domino read SRAM
    10.
    发明授权
    Split local and continuous bitline for fast domino read SRAM 有权
    分割本地和连续的位线快速多米诺骨牌SRAM

    公开(公告)号：US06657886B1

    公开(公告)日：2003-12-02

    申请号：US10140549

    申请日：2002-05-07

    申请人： Chad Allen Adams ,  Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Peter Thomas Freiburger

    发明人： Chad Allen Adams ,  Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Peter Thomas Freiburger

    IPC分类号： G11C1140

    CPC分类号： G11C11/419

    摘要： A high performance domino static random access memory (SRAM) is provided. The domino SRAM includes a plurality of local cell groups. Each of the plurality of local cell groups includes a plurality of SRAM cells and a local true bitline coupled to each of the plurality of SRAM cells of each local cell group. A continuous complement bitline is coupled to each of the plurality of local cell groups and is coupled to each of the plurality of SRAM cells of each local cell group. For a write to the SRAM cell complement node, only driving the continuous complement bitline is required. The domino SRAM reduces the number of required wires and required transistors as compared to prior art domino SRAM and thus the area needed and power consumption are reduced for the domino SRAM.

    摘要翻译： 提供了高性能的多米诺骨牌静态随机存取存储器（SRAM）。 多米诺SRAM包括多个本地小区组。 多个本地单元组中的每一个包括耦合到每个本地单元组的多个SRAM单元中的每一个的多个SRAM单元和本地真位线。 连续的补码位线耦合到多个局部单元组中的每一个，并耦合到每个本地单元组的多个SRAM单元中的每一个。 要写入SRAM单元补码节点，只需要驱动连续的补码位线。 与现有技术的多米诺骨牌SRAM相比，多米诺骨牌SRAM减少了所需的电线和所需的晶体管数量，因此为多米诺骨牌SRAM降低了所需的面积和功耗。