Abstract:
A coordinate detection input system includes two first elongated electric conductors with an insulation grounding device respectively, a control circuit and two elongated electric conductors with another insulation grounding device respectively. The two elongated electric conductors are disposed correspond to X-coordinate and Y-coordinate of the input system. The control circuit further includes a microprocessor, a field induced voltage transducer, an analog/digital converter and a signal transmission device. The elongated electric conductors are electrically connected to the microprocessor to induce electromagnetic fields sequentially every time after a zero checking has been done by the microprocessor. The field induced voltage transducer induces voltage in the magnetic field once the pulse current is operated to pass through any one of the electric conductors. The analog/digital converter transforms the induced voltages as coordinates and position of the field induced voltage transducer can be figured out accordingly.
Abstract:
A loop filter and a method for adjusting its compensating current to make a control voltage of the loop filter more stable. The loop filter includes a charge/discharge path for receiving a control current and constituted by a first resister and a capacitor, a second resistor connected to the first terminal of the first resistor, an OP amplifier having an output terminal connected to the second resistor, a first input terminal connected to the capacitor, and a second input terminal, and a compensating unit connected to the output and second terminals of the second resistor. The loop filter further comprises a current source to provide a compensating current to the compensating unit. The loop filter utilizes the compensating unit to compensate the offset between the two input terminals of the amplifier. Therefore, the loop current of the OP amplifier can be reduced or eliminated.
Abstract:
The present invention is described for compensating a signal which is transmitted by a transmitting module of the optical disk drive controller through a signal channel and received and reshaped by a receiving module of the optical pickup head to calibrate the duty cycle distortion occurred. The claimed method has the steps of providing a periodic test signal, and then delaying the periodic test signal to form an adjusted test signal and adjusting a delay of an edge between the periodic test signal and the adjusted test signal instructed by a calibration signal. Afterward, the method further has the steps of transmitting the adjusted test signal to the receiving module through the signal channel, and receiving and reshaping the adjusted test signal to form a received signal, and then generating a monitor signal, finally, the method has a step of generating the calibration signal in accordance with the monitor signal.
Abstract:
A processing method for ceramic, having processing steps consisting of: (a) Manufacture pellets; (b) Cover the pellets with microwave dielectric; (c) Place the pellets into a microwave environment; (d) Microwave degreasing; (e) Complete degreasing. Procedural steps of the present invention primarily consist of placing the ceramic pellets in a container filled with microwave dielectric powder, placing the container within the microwave environment, and then regulating microwave power and time period for degreasing, whereupon the microwave dielectric powder surrounding and covering the pellets subsequently absorbs the microwaves and thereby facilitates indirect degreasing of the pellets.
Abstract:
A signal calibration apparatus of a charge pump minimizes a current from the charge pump. The signal calibration apparatus includes a detecting circuit, a current adjusting circuit, and a calibrating circuit, wherein the detecting circuit is coupled to the charge pump for outputting a detecting signal according to the direction and magnitude of the current, the current adjusting circuit is coupled to the detecting circuit for outputting a calibrating signal according to the polarity and magnitude of the slew rate of the detecting signal; and the calibrating circuit, which consists of a first calibration current source and a second calibration current source, is respectively coupled to the charge pump and the current adjusting circuit for adjusting the first current and the second current by outputting a first calibrating current and second calibrating current to the charge pump.
Abstract:
A control circuit for an optical pickup head in an optical disk drive for outputting filtered signals. The control circuit includes a laser drive unit for receiving a laser control signal to control a laser light source to generate a laser beam with a specified power, a photo detector for receiving the laser beam reflected from an optical disk and outputting a plurality of light detection signals, and a filter unit for filtering out the high frequency components of the light detection signals and then outputs the filtered signals. Since the high frequency components have been suppressed in the filtered signals, the transmission distortion can be reduced when the filtered signals are transmitted to the optical disk drive controller through a flexible cable. Accordingly, a more stable wobble signal can be obtained by the optical disk drive controller to enhance the stability of the optical disk drive operation based on the filtered signals.
Abstract:
A single-transverse-mode VCSEL device with array structure and the fabrication method thereof. The single-transverse-mode VCSEL device with array structure comprises a plurality of light-emitting windows in a 1-D or 2-D array arrangement, and thereby provides high output power, low resistance, and a broad operating current range.
Abstract:
A phase locked loop (PLL), which has high operation speed and high resolution, and is particularly applicable in high frequency process, is disclosed. The PLL, receiving a data signal and generating a clock signal, comprises a voltage controlled oscillator (VCO) and multi-phase generator (MPG), a transition detector, an optimal phase encoder, and a phase selector, wherein the four devices are respectively used for outputting N phase clock signals of same frequency but different phases, for outputting a data period value and a clock period value by receiving the N phase clock signals, the data signal and the clock signal, for outputting a phase select signal according to the data period value and the clock period value, and for outputting one of the phase clock signals according to the phase select signal.
Abstract:
A redundant decoder having fuse-controlled transistor comprises as follows: a bistable circuit which outputs a pair of complementary signals; a discharging device which is turned on at an evaluating cycle to form a discharging path; a precharging device which is turned on at a precharging cycle before an evaluating cycle to provide a precharging voltage; a first pair of transistors, having first terminals coupled to the precharging voltage, first gate terminals coupled to receive pair of complementary signals whose logic values decide whether the first pair of transistors are turned on or not, and second terminals; a second pair of transistors, having third terminals coupled to the second terminals of the first pair of transistors, second gate terminals coupled to receive a pair of complementary address bit signals whose logic values decide whether the second pair of transistors are turned on or not, and fourth terminals coupled to the discharging device; and a fuse device, having a fuse which is coupled to the bistable device that decides the logic values of the pair of complementary signals by whether the fuse is burnt down or not.
Abstract:
A dynamic precharge redundant circuit for a semiconductor memory device. A PMOS transistor, a fuse, a first, second and third inverters, a first switch and a second switch are applied. A source of the PMOS transistor is coupled to a voltage supply, while a gate of the PMOS transistor is to receive a precharge signal. The fuse has a ground terminal and a terminal coupled to the drain of the PMOS transistor of which the drain is further coupled to an input terminal of the first inverter. The fuse is also coupled to a column address signal. The first inverter has an output terminal coupled to an input terminal of the first switch. The second inverter has an input terminal coupled to an output terminal of the first switch and an output terminal coupled to an input terminal of the third inverter, so as to output a bit-switch control signal. An input terminal of the second switch is coupled to an output terminal of the third inverter, while an output terminal of the second switch is coupled to both the output terminal of the first switch and the input terminal of the second inverter. Thus, an error caused by the generation of an interference signal of the bit-switch control signal is prevented, so as to prevent from damaging data of the bit line sense amplifier.