公开(公告)号：US09342305B2

公开(公告)日：2016-05-17

申请号：US14035177

申请日：2013-09-24

Applicant: Empire Technology Development LLC

Inventor： Yan Solihin

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/52

CPC classification number: G06F9/30043 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3851 ,  G06F9/4893 ,  G06F9/52 ,  Y02D10/24

Abstract: Technologies for low power execution of one or more threads of a multithreaded program by one or more processing elements are generally disclosed.

公开(公告)号：US20160117257A1

公开(公告)日：2016-04-28

申请号：US14859322

申请日：2015-09-20

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： Yan Solihin

IPC: G06F12/10

CPC classification number: G06F12/0646 ,  G06F12/0223 ,  G06F12/1009 ,  G06F12/109 ,  G06F17/30218 ,  G06F2212/401 ,  G06F2212/656 ,  G06F2212/657 ,  Y02D10/13

Abstract: Technologies are generally described herein for compressing an array using hardware-based compression and performing various instructions on the compressed array. Some example technologies may receive an instruction adapted to access an address in an array. The technologies may determine whether address is compressible. If the address is compressible, then the technologies may determine a compressed address of a compressed array based on the address. The compressed array may represent a compressed layout of the array where a reduced size of each compressed element in the compressed array is smaller than an original size of each element in the array. The technologies may access the compressed array at the compressed address in accordance with the instruction.

公开(公告)号：US09207980B2

公开(公告)日：2015-12-08

申请号：US14710307

申请日：2015-05-12

Applicant: Empire Technology Development LLC

Inventor： Yan Solihin

IPC: G06F9/46 ,  G06F9/48 ,  G06F12/08 ,  G06F9/50

CPC classification number: G06F9/4881 ,  G06F1/12 ,  G06F1/324 ,  G06F1/3287 ,  G06F9/5011 ,  G06F9/5088 ,  G06F12/0842 ,  G06F2212/6042 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/32

Abstract: Technologies are generally described for a multi-processor core and a method for transferring threads in a multi-processor core. In an example, a multi-core processor may include a first group including a first core and a second core. A first sum of the operating frequencies of the cores in the first group corresponds to a first total operating frequency. The multi-core processor may further include a second group including a third core. A second sum of the operating frequencies of the cores in the second group may correspond to a second total operating frequency that is substantially the same as the first total operating frequency. A hardware controller may be configured in communication with the first, second and third core. A memory may be configured in communication with the hardware controller and may include an indication of at least the first group and the second group.

Abstract translation: 技术通常被描述用于多处理器核心和用于在多处理器核心中传送线程的方法。 在一个示例中，多核处理器可以包括包括第一核和第二核的第一组。 第一组中的芯的工作频率的第一和对应于第一总操作频率。 多核处理器还可以包括包括第三核的第二组。 第二组中的芯的工作频率的第二和可以对应于与第一总操作频率基本相同的第二总工作频率。 硬件控制器可以被配置为与第一，第二和第三核心通信。 可以将存储器配置为与硬件控制器通信，并且可以包括至少第一组和第二组的指示。

公开(公告)号：US09158689B2

公开(公告)日：2015-10-13

申请号：US13982607

申请日：2013-02-11

Applicant: Empire Technology Development LLC

Inventor： Yan Solihin

IPC: G06F12/08

CPC classification number: G06F12/082 ,  G06F12/0817

Abstract: Technologies are described herein generally relate to aggregation of cache eviction notifications to a directory. Some example technologies may be utilized to update an aggregation table to reflect evictions of a plurality of blocks from a plurality of block addresses of at least one cache memory. An aggregate message can be generated, where the message specifies the evictions of the plurality of blocks as reflected in the aggregation table. The aggregate message can be sent to the directory. The directory can parse the aggregate message and update a plurality of directory entries to reflect the evictions from the cache memory as specified in the aggregate message.

Abstract translation: 本文中描述的技术通常涉及将缓存逐出通知集合到目录。 可以使用一些示例性技术来更新聚合表以反映从至少一个高速缓存存储器的多个块地址中的多个块的驱逐。 可以生成聚合消息，其中消息指定聚合表中反映的多个块的逐出。 聚合消息可以发送到目录。 该目录可以解析聚合消息并更新多个目录条目以反映聚合消息中指定的缓存中的驱逐。

公开(公告)号：US20150286577A1

公开(公告)日：2015-10-08

申请号：US14437331

申请日：2012-10-25

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： Yan Solihin

IPC: G06F12/08

CPC classification number: G06F12/0897 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0826 ,  G06F2212/1008 ,  G06F2212/1024 ,  G06F2212/251 ,  G06F2212/301

Abstract: Technologies are generally described for methods and systems effective to maintain coherence in a multi-core processor on a die. In an example, a method for processing a request for a particular block in a particular region may include analyzing, by a first processor, a first cache to determine whether there is a block indicator in the first cache associated with the particular block. The method may further include when the first processor determines that the block indicator is not present in the first cache, analyzing, by the first processor, the first cache to determine whether there is a region indicator associated with the particular region. The method may further include when the first processor determines that the region indicator is not present in the first cache, the method further includes sending, by the first processor, the request to the directory in the tile.

Abstract translation: 通常描述了有效地维持芯片上的多核处理器的相干性的方法和系统的技术。 在一个示例中，用于处理特定区域中的特定块的请求的方法可以包括由第一处理器分析第一高速缓存以确定与特定块相关联的第一高速缓存中是否存在块指示符。 该方法还可以包括当第一处理器确定块指示符不存在于第一高速缓存中时，由第一处理器分析第一高速缓存以确定是否存在与特定区域相关联的区域指示符。 该方法还可以包括当第一处理器确定区域指示符不存在于第一高速缓存中时，该方法还包括由第一处理器向盘中的目录发送请求。