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51.发明授权Signal processing circuit, inverter circuit, buffer circuit, level shifter, flip-flop, driver circuit, and display device 有权信号处理电路，逆变电路，缓冲电路，电平转换器，触发器，驱动电路和显示装置公开(公告)号：US08779809B2
公开(公告)日：2014-07-15
申请号：US13819400
申请日：2011-08-31
IPC分类号： H03K3/00
CPC分类号： H02J4/00 , H03K3/356008 , H03K3/356026 , H03K19/01714 , H03K19/01735 , Y10T307/50
摘要： A signal processing circuit of the present invention includes: first and second input terminals; an output terminal; a bootstrap capacitor; a first output section connected to the second input terminal and the output terminal; a second output section connected to the first input terminal, a first power source, and the output terminal; and an electric charge control section for controlling the electric charge of the bootstrap capacitor, the electric charge control section being connected to the first input terminal, the electric charge control section and the first output section being connected to each other via a relay section for either electrically connecting the electric charge control section and the first output section to each other or electrically blocking the electric charge control section and the first output section from each other, the electric charge control section including a resistor connected to a second power source. This configuration can increase reliability of a bootstrap-type signal processing circuit.
摘要翻译： 本发明的信号处理电路包括：第一和第二输入端; 输出端子; 自举电容器; 与第二输入端子和输出端子连接的第一输出部分; 连接到第一输入端子的第二输出部分，第一电源和输出端子; 以及用于控制自举电容器的电荷的电荷控制部分，所述电荷控制部分连接到所述第一输入端子，所述电荷控制部分和所述第一输出部分经由继电器部分彼此连接，用于任一 将电荷控制部和第一输出部彼此电连接，或者将电荷控制部和第一输出部彼此电阻塞，电荷控制部包括与第二电源连接的电阻。 该配置可以增加自举式信号处理电路的可靠性。
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52.发明授权公开(公告)号：US08736534B2
公开(公告)日：2014-05-27
申请号：US11922491
申请日：2006-07-11
IPC分类号： G09G3/36
CPC分类号： G09G3/3648 , G09G3/3688 , G09G2310/0245 , G09G2330/02 , G09G2330/027
摘要： In one embodiment of the present invention, on each source bus line, an electric charge escaping transistor is provided having the same polarity as a pixel transistor and having a gate to which a turn-off voltage signal of the pixel transistor is supplied. When an active matrix liquid crystal display device is powered off, the turn-off voltage signal is made to reach the GND level before a turn-on voltage signal of the pixel transistor reaches the GND level, so that the pixel transistor and the electric charge escaping transistor are made half-open. This lets electric charges accumulated in the pixel escape to a common electrode TCOM.
摘要翻译： 在本发明的一个实施例中，在每个源极总线上，设置电荷逸出晶体管，其具有与像素晶体管相同的极性，并且具有提供像素晶体管的关断电压信号的栅极。 当有源矩阵液晶显示装置断电时，在像素晶体管的导通电压信号达到GND电平之前，使关断电压信号达到GND电平，使得像素晶体管和电荷 逃逸晶体管制成半开放。 这使得在像素中累积的电荷逃逸到公共电极TCOM。
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53.发明申请SIGNAL PROCESSING CIRCUIT, INVERTER CIRCUIT, BUFFER CIRCUIT, DRIVER CIRCUIT, LEVEL SHIFTER, AND DISPLAY DEVICE 有权信号处理电路，逆变器电路，缓冲电路，驱动电路，电平变换器和显示装置公开(公告)号：US20130194033A1
公开(公告)日：2013-08-01
申请号：US13819043
申请日：2011-08-31
IPC分类号： G05F3/16
CPC分类号： G05F3/16 , G09G3/3674 , G09G2310/0286 , G09G2310/0291 , H04L25/0272
摘要： A signal processing circuit of the present invention includes: first and second input terminals; an output terminal; a bootstrap capacitor; a first output section connected to the second input terminal and the output terminal; a second output section connected to the first input terminal, a first power source, and the output terminal; an electric charge control section for controlling the electric charge of the bootstrap capacitor, the electric charge control section being connected to the first input terminal; and a resistor having (i) a first end connected to the output terminal and (ii) a second end connected to a second power source. This arrangement allows the signal processing circuit to maintain an output potential even after a bootstrap effect has worn off.
摘要翻译： 本发明的信号处理电路包括：第一和第二输入端; 输出端子; 自举电容器; 与第二输入端子和输出端子连接的第一输出部分; 连接到第一输入端子的第二输出部分，第一电源和输出端子; 用于控制所述自举电容器的电荷的电荷控制部分，所述电荷控制部分连接到所述第一输入端子; 以及电阻器，其具有（i）连接到所述输出端子的第一端和（ii）连接到第二电源的第二端。 这种布置允许信号处理电路即使在自举效应已经磨损之后仍然保持输出电位。
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公开(公告)号：US20130169319A1
公开(公告)日：2013-07-04
申请号：US13819827
申请日：2011-08-31
IPC分类号： H03K17/00
CPC分类号： H03K17/005 , G09G3/3677 , G09G2310/0286 , G09G2310/08 , G11C19/184 , G11C19/28 , H03K19/00315
摘要： A signal processing circuit of the present invention includes: a first input terminal; a second input terminal; a third input terminal; a first node; a second node; an output terminal; a resistor; a first signal generating section which (i) is connected to the first node, a third input terminal, and the output terminal and (ii) includes a bootstrap capacitor; and a second signal generating section which is connected to the second node, a first power supply, and the output terminal. The first node becomes active in a case where the first input terminal becomes active. The second node becomes active in a case where the second input terminal becomes active. The output terminal is connected to the first power supply via the resistor. With the configuration, it is possible to have an improvement in operational stability of the signal processing circuit.
摘要翻译： 本发明的信号处理电路包括：第一输入端; 第二输入端; 第三输入端; 第一个节点; 第二个节点; 输出端子; 一个电阻; （i）连接到第一节点的第一信号产生部分，第三输入端子和输出端子，以及（ii）包括自举电容器; 以及连接到第二节点的第二信号产生部分，第一电源和输出端子。 在第一输入端子变为活动状态的情况下，第一节点变为活动状态。 在第二输入端子变为活动状态的情况下，第二节点变为活动状态。 输出端子通过电阻连接到第一个电源。 利用该配置，可以改善信号处理电路的操作稳定性。
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55.发明授权Signal processing circuit, inverter circuit, buffer circuit, driver circuit, level shifter, and display device 有权信号处理电路，逆变电路，缓冲电路，驱动电路，电平转换器和显示装置公开(公告)号：US09024681B2
公开(公告)日：2015-05-05
申请号：US13819043
申请日：2011-08-31
CPC分类号： G05F3/16 , G09G3/3674 , G09G2310/0286 , G09G2310/0291 , H04L25/0272
摘要： A signal processing circuit of the present invention includes: first and second input terminals; an output terminal; a bootstrap capacitor; a first output section connected to the second input terminal and the output terminal; a second output section connected to the first input terminal, a first power source, and the output terminal; an electric charge control section for controlling the electric charge of the bootstrap capacitor, the electric charge control section being connected to the first input terminal; and a resistor having (i) a first end connected to the output terminal and (ii) a second end connected to a second power source. This arrangement allows the signal processing circuit to maintain an output potential even after a bootstrap effect has worn off.
摘要翻译： 本发明的信号处理电路包括：第一和第二输入端; 输出端子; 自举电容器; 与第二输入端子和输出端子连接的第一输出部分; 连接到第一输入端子的第二输出部分，第一电源和输出端子; 用于控制所述自举电容器的电荷的电荷控制部分，所述电荷控制部分连接到所述第一输入端子; 以及电阻器，其具有（i）连接到所述输出端子的第一端和（ii）连接到第二电源的第二端。 这种布置允许信号处理电路即使在自举效应已经磨损之后仍然保持输出电位。
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56.发明申请SIGNAL PROCESSING CIRCUIT, INVERTER CIRCUIT, BUFFER CIRCUIT, LEVEL SHIFTER, FLIP-FLOP, DRIVER CIRCUIT, AND DISPLAY DEVICE 有权信号处理电路，逆变器电路，缓冲电路，电平变换器，FLIP-FLOP，驱动电路和显示装置公开(公告)号：US20130154374A1
公开(公告)日：2013-06-20
申请号：US13819400
申请日：2011-08-31
IPC分类号： H02J4/00
CPC分类号： H02J4/00 , H03K3/356008 , H03K3/356026 , H03K19/01714 , H03K19/01735 , Y10T307/50
摘要： A signal processing circuit of the present invention includes: first and second input terminals; an output terminal; a bootstrap capacitor; a first output section connected to the second input terminal and the output terminal; a second output section connected to the first input terminal, a first power source, and the output terminal; and an electric charge control section for controlling the electric charge of the bootstrap capacitor, the electric charge control section being connected to the first input terminal, the electric charge control section and the first output section being connected to each other via a relay section for either electrically connecting the electric charge control section and the first output section to each other or electrically blocking the electric charge control section and the first output section from each other, the electric charge control section including a resistor connected to a second power source. This configuration can increase reliability of a bootstrap-type signal processing circuit.
摘要翻译： 本发明的信号处理电路包括：第一和第二输入端; 输出端子; 自举电容器; 与第二输入端子和输出端子连接的第一输出部分; 连接到第一输入端子的第二输出部分，第一电源和输出端子; 以及用于控制自举电容器的电荷的电荷控制部分，所述电荷控制部分连接到所述第一输入端子，所述电荷控制部分和所述第一输出部分经由继电器部分彼此连接，用于任一 将电荷控制部和第一输出部彼此电连接，或者将电荷控制部和第一输出部彼此电阻塞，电荷控制部包括与第二电源连接的电阻。 该配置可以提高自举式信号处理电路的可靠性。
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57.发明申请SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE UNIT, ACTIVE MATRIX SUBSTRATE, LIQUID CRYSTAL PANEL, AND LIQUID CRYSTAL DISPLAY 有权半导体器件，半导体器件单元，有源矩阵衬底，液晶面板和液晶显示器公开(公告)号：US20130153941A1
公开(公告)日：2013-06-20
申请号：US13819822
申请日：2011-08-26
CPC分类号： H01L28/40 , G02F1/13454 , G02F1/136277 , G09G3/3611 , G09G3/3648 , G09G2310/0278 , G09G2310/0286 , G09G2310/0291 , G09G2310/08 , H01L27/04 , H01L27/1255 , H01L33/08
摘要： A semiconductor device (10) provided with at least a plurality of transistors and bootstrap capacitors (Ca1 and Cb1), the semiconductor device (10) includes: a semiconductor layer (22) made of the same material as a channel layer of each of the transistors; a capacitor electrode (24) formed in an upper layer of the semiconductor layer (22); and a clock signal line (17) formed in an upper layer of the capacitor electrode (24), the capacitor electrode (24) being connected to a gate electrode of each of the transistors, the clock signal line (17) being supplied with a clock signal (CK) from outside the semiconductor device (10), the capacitors (Ca1 and Cb1) each being formed in an overlap section where the semiconductor layer (22), the gate insulating film (23) and the capacitor electrode (24) overlap one another, the overlap section and the clock signal line (17) overlapping each other when viewed from above.
摘要翻译： 设置有至少多个晶体管和自举电容器（Ca1和Cb1）的半导体器件（10），所述半导体器件（10）包括：由与所述半导体器件（10）的沟道层相同的材料制成的半导体层（22） 晶体管 形成在所述半导体层（22）的上层的电容电极（24）; 和形成在电容器电极（24）的上层的时钟信号线（17），电容电极（24）连接到每个晶体管的栅电极，时钟信号线（17）被提供有 来自半导体器件（10）外部的时钟信号（CK），在半导体层（22），栅极绝缘膜（23）和电容器电极（24）的重叠部分中形成的电容器（Ca1和Cb1） 彼此重叠，当从上方观看时，重叠部分和时钟信号线（17）彼此重叠。
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58.发明申请公开(公告)号：US20090085902A1
公开(公告)日：2009-04-02
申请号：US11922491
申请日：2006-07-11
CPC分类号： G09G3/3648 , G09G3/3688 , G09G2310/0245 , G09G2330/02 , G09G2330/027
摘要： In one embodiment of the present invention, on each source bus line, an electric charge escaping transistor is provided having the same polarity as a pixel transistor and having a gate to which a turn-off voltage signal of the pixel transistor is supplied. When an active matrix liquid crystal display device is powered off, the turn-off voltage signal is made to reach the GND level before a turn-on voltage signal of the pixel transistor reaches the GND level, so that the pixel transistor and the electric charge escaping transistor are made half-open. This lets electric charges accumulated in the pixel escape to a common electrode TCOM.
摘要翻译： 在本发明的一个实施例中，在每个源极总线上，设置电荷逸出晶体管，其具有与像素晶体管相同的极性，并且具有提供像素晶体管的截止电压信号的栅极。 当有源矩阵液晶显示装置断电时，在像素晶体管的导通电压信号达到GND电平之前，使关断电压信号达到GND电平，使得像素晶体管和电荷 逃逸晶体管制成半开放。 这使得在像素中累积的电荷逃逸到公共电极TCOM。
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59.发明授权Shift register including unit circuits connected in multistage manner, and display device 有权移位寄存器，包括以多级方式连接的单元电路和显示设备公开(公告)号：US09390813B2
公开(公告)日：2016-07-12
申请号：US13818462
申请日：2011-08-30
CPC分类号： G11C19/28 , G09G3/3677 , G09G2310/0286
摘要： A unit circuit (11) includes: a transistor (T2) having its drain terminal to be supplied with a clock signal (CK) and its source terminal connected to an output terminal (OUT); a transistor (T9) which, when supplied with an active all-on control signal (AON), outputs an ON voltage to the output terminal (OUT), and which, when supplied with a nonactive all-on control signal (AONB), stops outputting the ON voltage; a transistor (T1) which supplies the ON voltage to a control terminal of the transistor (T2) in accordance with an input signal (IN); a transistor (T4) which, when supplied with the active all-on control signal (AON), supplies an OFF voltage to a control terminal of the transistor (T2). This makes it possible to provide a shift register of a simple structure that can prevent a malfunction from occurring after all-on operation, and to provide a display device.
摘要翻译： 单元电路（11）包括：晶体管（T2），其漏极端子被提供有时钟信号（CK），其源极端子连接到输出端子（OUT）; 当提供有源全通控制信号（AON）时，将晶体管（T9）输出到输出端（OUT）的导通电压，并且当被提供有非活动全通控制信号（AONB）时， 停止输出ON电压; 晶体管（T1），其根据输入信号（IN）将导通电压提供给晶体管（T2）的控制端子; 当提供有源全通控制信号（AON）时，晶体管（T4）向晶体管（T2）的控制端提供OFF电压。 这使得可以提供能够防止在全部操作之后发生故障的简单结构的移位寄存器，并且提供显示装置。
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60.发明授权Semiconductor device, semiconductor device unit, active matrix substrate, liquid crystal panel, and liquid crystal display 有权半导体器件，半导体器件单元，有源矩阵基板，液晶面板和液晶显示器公开(公告)号：US09076756B2
公开(公告)日：2015-07-07
申请号：US13819822
申请日：2011-08-26
IPC分类号： H01L29/18 , H01L33/00 , H01L21/02 , H01L49/02 , G09G3/36 , H01L27/04 , H01L33/08 , H01L27/12 , G02F1/1345 , G02F1/1362
CPC分类号： H01L28/40 , G02F1/13454 , G02F1/136277 , G09G3/3611 , G09G3/3648 , G09G2310/0278 , G09G2310/0286 , G09G2310/0291 , G09G2310/08 , H01L27/04 , H01L27/1255 , H01L33/08
摘要： A semiconductor device (10) provided with at least a plurality of transistors and bootstrap capacitors (Ca1 and Cb1), the semiconductor device (10) includes: a semiconductor layer (22) made of the same material as a channel layer of each of the transistors; a capacitor electrode (24) formed in an upper layer of the semiconductor layer (22); and a clock signal line (17) formed in an upper layer of the capacitor electrode (24), the capacitor electrode (24) being connected to a gate electrode of each of the transistors, the clock signal line (17) being supplied with a clock signal (CK) from outside the semiconductor device (10), the capacitors (Ca1 and Cb1) each being formed in an overlap section where the semiconductor layer (22), the gate insulating film (23) and the capacitor electrode (24) overlap one another, the overlap section and the clock signal line (17) overlapping each other when viewed from above.
摘要翻译： 设置有至少多个晶体管和自举电容器（Ca1和Cb1）的半导体器件（10），所述半导体器件（10）包括：由与所述半导体器件（10）的沟道层相同的材料制成的半导体层（22） 晶体管 形成在所述半导体层（22）的上层的电容电极（24）; 和形成在电容器电极（24）的上层的时钟信号线（17），电容电极（24）连接到每个晶体管的栅电极，时钟信号线（17）被提供有 来自半导体器件（10）外部的时钟信号（CK），在半导体层（22），栅极绝缘膜（23）和电容器电极（24）的重叠部分中形成的电容器（Ca1和Cb1） 彼此重叠，当从上方观察时，重叠部分和时钟信号线（17）彼此重叠。
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