-
1.发明授权公开(公告)号：US08736534B2
公开(公告)日：2014-05-27
申请号：US11922491
申请日：2006-07-11
IPC分类号： G09G3/36
CPC分类号： G09G3/3648 , G09G3/3688 , G09G2310/0245 , G09G2330/02 , G09G2330/027
摘要： In one embodiment of the present invention, on each source bus line, an electric charge escaping transistor is provided having the same polarity as a pixel transistor and having a gate to which a turn-off voltage signal of the pixel transistor is supplied. When an active matrix liquid crystal display device is powered off, the turn-off voltage signal is made to reach the GND level before a turn-on voltage signal of the pixel transistor reaches the GND level, so that the pixel transistor and the electric charge escaping transistor are made half-open. This lets electric charges accumulated in the pixel escape to a common electrode TCOM.
摘要翻译： 在本发明的一个实施例中，在每个源极总线上，设置电荷逸出晶体管，其具有与像素晶体管相同的极性，并且具有提供像素晶体管的关断电压信号的栅极。 当有源矩阵液晶显示装置断电时，在像素晶体管的导通电压信号达到GND电平之前，使关断电压信号达到GND电平，使得像素晶体管和电荷 逃逸晶体管制成半开放。 这使得在像素中累积的电荷逃逸到公共电极TCOM。
-
公开(公告)号：US20120169751A1
公开(公告)日：2012-07-05
申请号：US13395681
申请日：2010-05-18
申请人： Etsuo Yamamoto , Yasushi Sasaki , Yuhichiroh Murakami , Shige Furuta , Seijirou Gyouten , Shuji Nishi
发明人： Etsuo Yamamoto , Yasushi Sasaki , Yuhichiroh Murakami , Shige Furuta , Seijirou Gyouten , Shuji Nishi
CPC分类号： G09G3/3648 , G02F1/13624 , G09G3/3614 , G09G2300/0857 , G09G2310/08 , G09G2320/0219 , G09G2330/021
摘要： In an active matrix display apparatus including: pixels provided in a matrix pattern, the pixels each including a memory circuit which retains data while refreshing the data, a data signal electric potential which is supplied from a source line in a period t1 and written to a node which is connected to a liquid capacitor is higher than a data electric potential of the node, the data electric potential being obtained in a period t14 after a refresh operation of the memory circuit.
摘要翻译： 在一种有源矩阵显示装置中，包括以矩阵模式提供的像素，每个像素包括一个在刷新数据的同时保留数据的存储电路，在时间段t1内从源极线提供的数据信号电位被写入到 连接到液体电容器的节点高于节点的数据电位，在存储器电路的刷新操作之后的周期t14中获得数据电位。
-
3.发明申请公开(公告)号：US20090085902A1
公开(公告)日：2009-04-02
申请号：US11922491
申请日：2006-07-11
CPC分类号： G09G3/3648 , G09G3/3688 , G09G2310/0245 , G09G2330/02 , G09G2330/027
摘要： In one embodiment of the present invention, on each source bus line, an electric charge escaping transistor is provided having the same polarity as a pixel transistor and having a gate to which a turn-off voltage signal of the pixel transistor is supplied. When an active matrix liquid crystal display device is powered off, the turn-off voltage signal is made to reach the GND level before a turn-on voltage signal of the pixel transistor reaches the GND level, so that the pixel transistor and the electric charge escaping transistor are made half-open. This lets electric charges accumulated in the pixel escape to a common electrode TCOM.
摘要翻译： 在本发明的一个实施例中，在每个源极总线上，设置电荷逸出晶体管，其具有与像素晶体管相同的极性，并且具有提供像素晶体管的截止电压信号的栅极。 当有源矩阵液晶显示装置断电时，在像素晶体管的导通电压信号达到GND电平之前，使关断电压信号达到GND电平，使得像素晶体管和电荷 逃逸晶体管制成半开放。 这使得在像素中累积的电荷逃逸到公共电极TCOM。
-
公开(公告)号：US08896511B2
公开(公告)日：2014-11-25
申请号：US13395681
申请日：2010-05-18
申请人： Etsuo Yamamoto , Yasushi Sasaki , Yuhichiroh Murakami , Shige Furuta , Seijirou Gyouten , Shuji Nishi
发明人： Etsuo Yamamoto , Yasushi Sasaki , Yuhichiroh Murakami , Shige Furuta , Seijirou Gyouten , Shuji Nishi
IPC分类号： G09G3/36 , G09G5/00 , G02F1/1362
CPC分类号： G09G3/3648 , G02F1/13624 , G09G3/3614 , G09G2300/0857 , G09G2310/08 , G09G2320/0219 , G09G2330/021
摘要： In an active matrix display apparatus including: pixels provided in a matrix pattern, the pixels each including a memory circuit which retains data while refreshing the data, a data signal electric potential which is supplied from a source line in a period t1 and written to a node which is connected to a liquid capacitor is higher than a data electric potential of the node, the data electric potential being obtained in a period t14 after a refresh operation of the memory circuit.
摘要翻译： 在一种有源矩阵显示装置中，包括以矩阵模式提供的像素，每个像素包括一个在刷新数据的同时保留数据的存储电路，在时间段t1内从源极线提供的数据信号电位被写入到 连接到液体电容器的节点高于节点的数据电位，在存储器电路的刷新操作之后的周期t14中获得数据电位。
-
公开(公告)号：US08427206B2
公开(公告)日：2013-04-23
申请号：US12734691
申请日：2008-08-19
IPC分类号： H03K3/00
CPC分类号： G09G3/3677 , G09G2310/0291 , G09G2330/021 , H03K19/0013 , H03K19/01714 , H03K19/018507 , H03K19/09441
摘要： A single-phase input including transistors all of which have only a single type of channel polarity, which buffer includes: a buffer section 32, including a first series circuit formed by two n-channel transistors connected to each other in series, a second series circuit formed by two n-channel transistors connected to each other in series at a connection point OUT, and a capacitor; and an inverted-signal generating section for generating an inverted-signal from an input signal, the inverted-signal generating section including n-channel transistors but no p-channel transistor, the input signal being inputted to respective gates of the transistors, the inverted-signal being inputted to a gate of the transistor 4, and an output signal being outputted via the connection point OUT. With the buffer, it is possible that a consumption current be reduced and a current drive for a load is enhanced.
摘要翻译： 包括晶体管的单相输入，所述晶体管仅具有单一类型的沟道极性，该缓冲器包括：缓冲器部分32，包括由串联连接的两个n沟道晶体管构成的第一串联电路，第二系列 由在连接点OUT处彼此串联连接的两个n沟道晶体管形成的电路，以及电容器; 以及反相信号生成部，用于从输入信号产生反相信号，所述反相信号生成部包括n沟道晶体管，但不包括p沟道晶体管，所述输入信号被输入到所述晶体管的各个栅极，所述反相信号生成部 信号被输入到晶体管4的栅极，并且输出信号经由连接点OUT输出。 使用缓冲器，可以减少消耗电流并且增加用于负载的电流驱动。
-
公开(公告)号：US20120200549A1
公开(公告)日：2012-08-09
申请号：US13395518
申请日：2010-04-23
CPC分类号： G09G3/3659 , G09G2300/0842 , G09G2300/0861 , G09G2320/0219 , G09G2330/022
摘要： Provided is a display device which can prevent screen noise caused such that a potential of a common electrode is reversed after a memory mode enters from a refresh period to an entire write-in period, and a method for driving the display device. The memory mode includes (i) an entire write-in period in which a potential of the common electrode (COM) is fixed and the display data is written into all the memory circuits (node (PIX)) in each row and (ii) a refresh period in which the display data which has been written during the entire write-in period is refreshed at least once while the common electrode (COM) is driven. In the memory mode, the potential of the common electrode during the entire write-in period being a potential which the common electrode having been driven had at the end of a refresh period preceding the entire write-in period.
摘要翻译： 提供一种显示装置，其可以防止在从刷新周期进入整个写入周期之后引起公共电极的电位反转的屏幕噪声，以及用于驱动显示装置的方法。 存储模式包括：（i）公共电极（COM）的电位固定并将显示数据写入到每行的所有存储电路（节点（PIX））中的整个写入周期，以及（ii） 在驱动公共电极（COM）的过程中至少刷新一次整个写入周期期间已写入的显示数据的刷新周期。 在存储模式中，公共电极在整个写入周期期间的电位是已经被驱动的公共电极在整个写入周期之前的刷新周期结束时的电位。
-
7.发明申请MEMORY DEVICE, DISPLAY DEVICE EQUIPPED WITH MEMORY DEVICE, DRIVE METHOD FOR MEMORY DEVICE, AND DRIVE METHOD FOR DISPLAY DEVICE 有权存储装置，具有存储装置的显示装置，用于存储装置的驱动方法和用于显示装置的驱动方法公开(公告)号：US20120169753A1
公开(公告)日：2012-07-05
申请号：US13496027
申请日：2010-04-23
CPC分类号： G09G3/3659 , G09G2300/0417 , G09G2300/0823 , G09G2300/0842 , G09G2300/0861 , G09G2300/088 , G09G2330/022 , G11C11/405
摘要： A memory device is provided which includes a memory circuit that allows a circuit which carries out a refresh operation to suitably carry out an original operation of the circuit even if an off-leakage current occurs in a transfer element used in a transfer section. A memory cell includes a switching circuit, a first retaining section, a transfer section, a second retaining section, a first control section, and a voltage supply, and the first control section is controlled to be in (i) a state in which the first control section carries out a first operation in which the first control section is in an active state or a non-active state and (ii) a state in which the first control section carries out a second operation.
摘要翻译： 提供了一种存储器件，其包括一个存储器电路，即使在转印部件中使用的转印元件中出现泄漏电流，允许进行刷新操作的电路适当地执行电路的原始操作。 存储单元包括开关电路，第一保持部分，转移部分，第二保持部分，第一控制部分和电压源，并且第一控制部分被控制为处于（i） 第一控制部分执行第一操作，其中第一控制部分处于活动状态或非活动状态，以及（ii）第一控制部分执行第二操作的状态。
-
8.发明授权公开(公告)号：US08866719B2
公开(公告)日：2014-10-21
申请号：US13395549
申请日：2010-05-18
IPC分类号： G09G3/36 , H01L27/108 , G11C11/406 , H01L27/12
CPC分类号： H01L27/108 , G09G3/3614 , G09G3/3618 , G09G3/3648 , G09G3/3659 , G09G2300/0823 , G09G2300/0852 , G09G2330/021 , G11C11/406 , G11C2211/4067 , H01L27/12
摘要： A transistor (N1) has a gate terminal connected to a word line (Xi(1)) and a first conduction terminal connected to a bit line (Yj). A transistor (N2) has a gate terminal connected to the word line (Xi(2)) and a first conduction terminal connected to a node (PIX). A transistor (N3) has a gate terminal connected to a node (MRY) and a first conduction terminal connected to the word line (Xi(2)). A transistor (N4) has a gate terminal connected to the word line (Xi(3)), a first conduction terminal connected to a second conduction terminal of the transistor (N3), and a second conduction terminal connected to the node (PIX). Capacitors (Ca1), (Cb1), (Cap1) are formed between the node (PIX) and a reference electric potential wire (RL1), between the node (MRY) and the reference electric potential wire (RL1), and between the first conduction terminal of the transistor (N3) and the node (MRY), respectively.
摘要翻译： 晶体管（N1）具有连接到字线（Xi（1））的栅极端子和连接到位线（Yj）的第一导电端子。 晶体管（N2）具有连接到字线（Xi（2））的栅极端子和连接到节点（PIX）的第一导电端子。 晶体管（N3）具有连接到节点（MRY）的栅极端子和连接到字线（Xi（2））的第一导电端子。 晶体管（N4）具有连接到字线（Xi（3））的栅极端子，连接到晶体管（N3）的第二导通端子的第一导电端子和连接到节点（PIX）的第二导电端子， 。 在节点（MRY）和参考电位线（RL1）之间以及在第一（VI））之间的节点（PIX）和参考电位线（RL1）之间形成电容器（Ca1），（Cb1） 晶体管（N3）和节点（MRY）的导通端子。
-
9.发明授权Memory device, display device equipped with memory device, drive method for memory device, and drive method for display device 有权存储装置，配备有存储装置的显示装置，存储装置的驱动方法以及显示装置的驱动方法公开(公告)号：US08775842B2
公开(公告)日：2014-07-08
申请号：US13395739
申请日：2010-05-18
IPC分类号： G06F1/32
CPC分类号： G09G3/3659 , G09G2300/0857 , G09G2310/08 , G09G2320/0219 , G09G2330/022
摘要： A memory device can perform a first operation mode in which a discrete level is supplied to cause the memory cell to retain a logical level, and prevent unnecessary power consumption due to an operation of a power source which is unnecessary in the first operation mode. The memory device includes: a first power source for supplying a first potential level; a second power source for supplying a second potential level, a third power source for supplying a potential higher than a highest potential of discrete levels; and a fourth power source for supplying a potential lower than a lowest potential of the discrete levels, the first and second potential levels being used to supply the discrete levels, when the first operation is carried out, VDD, VSS, and GVDD being caused to be in operation and the fourth power source being stopped from being in operation.
摘要翻译： 存储器件可以执行其中提供离散电平以使存储器单元保持逻辑电平的第一操作模式，并且防止由于在第一操作模式中不必要的电源的操作引起的不必要的功耗。 存储器件包括：用于提供第一电位电平的第一电源; 用于提供第二电位电平的第二电源，用于提供高于离散电平的最高电位的电位的第三电源; 以及用于提供低于所述离散电平的最低电位的电位的第四电源，所述第一和第二电位电平用于提供所述离散电平，当执行所述第一操作时，引起VDD，VSS和GVDD 运行中，第四个电源停止工作。
-
10.发明申请MEMORY DEVICE, DISPLAY DEVICE EQUIPPED WITH MEMORY DEVICE, DRIVE METHOD FOR MEMORY DEVICE, AND DRIVE METHOD FOR DISPLAY DEVICE 有权存储装置，具有存储装置的显示装置，用于存储装置的驱动方法和用于显示装置的驱动方法公开(公告)号：US20120179923A1
公开(公告)日：2012-07-12
申请号：US13395739
申请日：2010-03-18
IPC分类号： G06F1/26
CPC分类号： G09G3/3659 , G09G2300/0857 , G09G2310/08 , G09G2320/0219 , G09G2330/022
摘要： A memory device can perform a first operation mode in which a discrete level is supplied to cause the memory cell to retain a logical level, and prevent unnecessary power consumption due to an operation of a power source which is unnecessary in the first operation mode. The memory device includes: a first power source (VDD) for supplying a first potential level; a second power source (VSS) for supplying a second potential level, a third power source (GVDD) for supplying a potential higher than a highest potential of discrete levels; and a fourth power source for supplying a potential lower than a lowest potential of the discrete levels, the first and second potential levels being used to supply the discrete levels, when the first operation is carried out, VDD, VSS, and GVDD being caused to be in operation and the fourth power source being stopped from being in operation.
摘要翻译： 存储器件可以执行其中提供离散电平以使存储器单元保持逻辑电平的第一操作模式，并且防止由于在第一操作模式中不必要的电源的操作引起的不必要的功耗。 存储器件包括：用于提供第一电位电平的第一电源（VDD）; 用于提供第二电位电平的第二电源（VSS）;用于提供高于离散电平的最高电位的电位的第三电源（GVDD）; 以及用于提供低于所述离散电平的最低电位的电位的第四电源，所述第一和第二电位电平用于提供所述离散电平，当执行所述第一操作时，引起VDD，VSS和GVDD 运行中，第四个电源停止工作。
-
-
-
-
-
-
-
-
-
搜索结果
206 条记录 (耗时 0.024 秒)
