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59 条记录 (耗时 0.027 秒)

    Cascaded gate-driven ESD clamp
    51.
    发明授权
    Cascaded gate-driven ESD clamp 有权
    级联门驱动ESD钳位

    公开(公告)号：US07221551B2

    公开(公告)日：2007-05-22

    申请号：US10866453

    申请日：2004-06-11

    申请人： Ker-Min Chen

    发明人： Ker-Min Chen

    IPC分类号： H01T23/00 ,  H02H3/22 ,  H02H9/00 ,  H02H3/20 ,  H02H9/04

    CPC分类号： H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method is provided for semiconductor ESD protection in a mixed voltage device using a cascaded gate driven NMOS clamp circuit. Use of a bias circuit allows for an external I/O signal to have a voltage higher than the internal circuit power supply voltage so that a proper trigger level is provided in reference to an external power supply reference. A cascaded gate NMOS clamp circuit dissipates charge from an ESD event from the higher external I/O signal level without interfering with the normal operation of the internal or “core” circuits.

    摘要翻译： 在使用级联栅极驱动的NMOS钳位电路的混合电压装置中提供半导体ESD保护的方法。 使用偏置电路允许外部I / O信号具有高于内部电路电源电压的电压，从而参考外部电源参考提供适当的触发电平。 级联栅极NMOS钳位电路从较高的外部I / O信号电平消耗来自ESD事件的电荷，而不会干扰内部或“内部”电路的正常工作。

    ESD protection system for multiple-domain integrated circuits
    52.
    发明申请
    ESD protection system for multiple-domain integrated circuits 有权
    多域集成电路的ESD保护系统

    公开(公告)号：US20070085144A1

    公开(公告)日：2007-04-19

    申请号：US11252468

    申请日：2005-10-17

    申请人： Ker-Min Chen

    发明人： Ker-Min Chen

    IPC分类号： H01L23/62

    CPC分类号： H01L27/0251 ,  H01L27/0292 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit system includes a first device in a first power domain, and a second device coupled to the first device in a second power domain. A circuit module is coupled between the first device and a power supply voltage or between the first device and a complementary power supply voltage in the first power domain for increasing an impedance against an ESD current flowing from the first device to the second device during an ESD event.

    摘要翻译： 集成电路系统包括第一电源域中的第一设备和在第二电源域中耦合到第一设备的第二设备。 电路模块耦合在第一设备和电源电压之间，或者耦合在第一电源域中的第一设备和互补电源电压之间，用于在ESD期间增加针对从第一设备流向第二设备的ESD电流的阻抗 事件。

    Boost-biased level shifter
    53.
    发明授权
    Boost-biased level shifter 有权
    升压偏置电平转换器

    公开(公告)号：US07151400B2

    公开(公告)日：2006-12-19

    申请号：US10889724

    申请日：2004-07-13

    申请人： Ker-Min Chen

    发明人： Ker-Min Chen

    IPC分类号： H03L5/00

    CPC分类号： H03K3/356113 ,  H03K17/102

    摘要： A boost-biased level shifter is described. In the preferred embodiments of the present invention, a voltage divider circuit divides the high voltage applied on the receiver circuit that receives the input signal, a refresh and self-bias circuit maintains and refreshes a bias voltage that is high enough to turn on the transistors in the voltage divider circuit, and a voltage output circuit outputs a signal having the amplitude of a higher power supply source, which is higher than the input signal amplitude. The preferred embodiments can operate at input signals having a lower amplitude. The performance is improved.

    摘要翻译： 描述了升压偏置电平转换器。 在本发明的优选实施例中，分压器电路分压接收输入信号的接收器电路上施加的高电压，刷新和自偏置电路维持和刷新高达足以导通晶体管的偏置电压 在分压电路中，电压输出电路输出高于输入信号幅度的具有较高电源的振幅的信号。 优选的实施例可以在具有较低振幅的输入信号下工作。 表现有所改善。

    Boost-biased level shifter
    56.
    发明申请
    Boost-biased level shifter 有权

    公开(公告)号：US20060012415A1

    公开(公告)日：2006-01-19

    申请号：US10889724

    申请日：2004-07-13

    申请人： Ker-Min Chen

    发明人： Ker-Min Chen

    IPC分类号： H03L5/00

    CPC分类号： H03K3/356113 ,  H03K17/102

    摘要： A boost-biased level shifter is described. In the preferred embodiments of the present invention, a voltage divider circuit divides the high voltage applied on the receiver circuit that receives the input signal, a refresh and self-bias circuit maintains and refreshes a bias voltage that is high enough to turn on the transistors in the voltage divider circuit, and a voltage output circuit outputs a signal having the amplitude of a higher power supply source, which is higher than the input signal amplitude. The preferred embodiments can operate at input signals having a lower amplitude. The performance is improved.

    USB interface and testing method thereof
    58.
    发明申请
    USB interface and testing method thereof 审中-公开
    USB接口及其测试方法

    公开(公告)号：US20050097403A1

    公开(公告)日：2005-05-05

    申请号：US10689408

    申请日：2003-10-20

    申请人： Ker-Min Chen

    发明人： Ker-Min Chen

    IPC分类号： G06F11/00

    CPC分类号： G06F11/221

    摘要： A physical layer of a USB interface. A test signal generator generates a test signal. A signal sampling device coupled to the test signal generator samples the test signal and outputs the test signal after a predetermined time. A transmitter and a receiver coupled to a signal access the data of the transmission terminals. A USB transceiver macrocell coupled to the test signal generator, the transmitter and receiver converts the test signal to USB protocol, outputs a first converted signal through the transmitter, receives the first converted signal through the transmission terminals and the receiver, and converts the received first converted signal to a second converted signal. A comparator coupled to the USB transceiver macrocell and the signal sampling device compares the second converted signal with the test signal, and outputs an error acknowledging signal.

    摘要翻译： USB接口的物理层。 测试信号发生器产生测试信号。 耦合到测试信号发生器的信号采样设备对测试信号进行采样并在预定时间之后输出测试信号。 耦合到信号的发射机和接收机接收传输终端的数据。 USB收发器宏单元耦合到测试信号发生器，发送器和接收器将测试信号转换为USB协议，通过发送器输出第一转换信号，通过发送端和接收器接收第一转换信号，并将接收的第一 转换后的信号转换为第二转换信号。 耦合到USB收发器宏单元的比较器和信号采样装置将第二转换信号与测试信号进行比较，并输出错误确认信号。

    Circuit to eliminate bus contention at chip power up
    59.
    发明授权
    Circuit to eliminate bus contention at chip power up 有权
    在芯片上电时消除总线争用的电路

    公开(公告)号：US06563353B2

    公开(公告)日：2003-05-13

    申请号：US10100051

    申请日：2002-03-19

    申请人： Ker-Min Chen ,  Wen-Tai Wang

    发明人： Ker-Min Chen ,  Wen-Tai Wang

    IPC分类号： H03L700

    CPC分类号： H03K17/223

    摘要： A power-on control circuit for an integrated circuit of the type having plural voltage source. The circuit is powered on sequentially, thereby preventing bus contention. The power-on control circuit includes a power-on detection for generating an enabling signal and disabling signal to control output buffer. When the high voltage source is powered on and the low voltage is not, the output buffer is at a high impedance state to prevent bus contention. When the low voltage is powered on after the high voltage is powered on, the output buffer is at a normal state.

    摘要翻译： 一种具有多个电压源的集成电路的通电控制电路。 电路依次通电，从而防止总线争用。 上电控制电路包括用于产生使能信号的电源接通检测和禁止信号以控制输出缓冲器。 当高压电源通电且低电压不工作时，输出缓冲器处于高阻抗状态，以防止总线冲突。 高电压上电后，低电压通电时，输出缓冲器处于正常状态。