公开(公告)号：US20100026366A1

公开(公告)日：2010-02-04

申请号：US12494082

申请日：2009-06-29

申请人： Guang-Cheng Wang ,  Ker-Min Chen ,  Kuo-Ji Chen

发明人： Guang-Cheng Wang ,  Ker-Min Chen ,  Kuo-Ji Chen

IPC分类号： H03L5/00

CPC分类号： H03K3/35613 ,  H03K3/012

摘要： A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a switching device coupled between a drain of one of the pair of PMOS transistors and a drain of the NMOS transistor, wherein the pair of PMOS transistors are high voltage transistors and the switching device is off when the VCCL is below a predetermined voltage level, and the switching device is on when the VCCL is above the predetermined voltage level.

摘要翻译： 公开了一种具有内部低压电源（VCCL）和外部高压电源（VCCH）的集成电路系统的电压电平移动电路，电压电平移位电路包括一对连接到VCCH的交叉耦合PMOS晶体管 ，源极连接到地（VSS）的NMOS晶体管和连接到在VCCL和VSS之间摆动的第一信号的栅极，以及耦合在一对PMOS晶体管之一的漏极和 NMOS晶体管，其中一对PMOS晶体管是高压晶体管，并且当VCCL低于预定电压电平时，开关器件关断，并且当VCCL高于预定电压电平时，开关器件导通。

公开(公告)号：US07649214B2

公开(公告)日：2010-01-19

申请号：US11252468

申请日：2005-10-17

申请人： Ker-Min Chen

发明人： Ker-Min Chen

IPC分类号： H01L23/60

CPC分类号： H01L27/0251 ,  H01L27/0292 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit system includes a first device in a first power domain, and a second device coupled to the first device in a second power domain. A circuit module is coupled between the first device and a power supply voltage or between the first device and a complementary power supply voltage in the first power domain for increasing an impedance against an ESD current flowing from the first device to the second device during an ESD event.

摘要翻译： 集成电路系统包括第一电源域中的第一设备和在第二电源域中耦合到第一设备的第二设备。 电路模块耦合在第一设备和电源电压之间，或者耦合在第一电源域中的第一设备和互补电源电压之间，用于在ESD期间增加针对从第一设备流向第二设备的ESD电流的阻抗 事件。

公开(公告)号：US20080184174A1

公开(公告)日：2008-07-31

申请号：US11626951

申请日：2007-01-25

申请人： Ker-Min Chen

发明人： Ker-Min Chen

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/04

摘要： One embodiment is a method of designing an integrated circuit (“IC”) using an online design platform system comprising a design platform provider, at least one electronic design automation (“EDA”) tool and at least one intellectual property (“IP”) library. The method comprises accessing the design platform provider using a computer remote from the design platform provider, wherein the remote computer is connected to the design platform provider and the accessing occurs via an Internet connection; providing access via the remote computer to the at least one EDA tool and the at least one IP library for enabling a user at the remote computer to design an IC; and providing at least one file comprising a final design of the IC directly from the online design platform system to a designated foundry.

摘要翻译： 一个实施例是使用包括设计平台提供商，至少一个电子设计自动化（“EDA”）工具和至少一个知识产权（“IP”）的在线设计平台系统来设计集成电路（“IC”）的方法， 图书馆。 该方法包括使用远离设计平台提供商的计算机访问设计平台提供商，其中远程计算机连接到设计平台提供商，并且通过因特网连接进行访问; 通过所述远程计算机向所述至少一个EDA工具和所述至少一个IP库提供访问，以使所述远程计算机上的用户能够设计IC; 以及将包括IC的最终设计的至少一个文件直接从在线设计平台系统提供给指定的代工厂。

公开(公告)号：US07362136B2

公开(公告)日：2008-04-22

申请号：US11397213

申请日：2006-04-04

申请人： Ker-Min Chen

发明人： Ker-Min Chen

IPC分类号： H03K19/094

CPC分类号： H03K19/018521

摘要： An I/O output circuit is disclosed for interfacing a first system operating at a first voltage with a second system operating at a second voltage higher than the first voltage. The I/O output circuit includes an output stage module having one or more PMOS transistors and one or more NMOS transistors for coupling with the second system. A switch module is coupled to the output stage module for selectively providing the PMOS and NMOS transistors with various gate biases. A feedback circuit is coupled between an I/O pad that couples the output stage module to the second system and the switch module for controlling the switch module to generate the gate biases in response to a voltage at the I/O pad, thereby ensuring voltages across gates of the PMOS and NMOS transistors to be within a predetermined range.

摘要翻译： 公开了一种I / O输出电路，用于将以第一电压工作的第一系统与以比第一电压高的第二电压工作的第二系统进行接口。 I / O输出电路包括具有一个或多个PMOS晶体管和用于与第二系统耦合的一个或多个NMOS晶体管的输出级模块。 开关模块耦合到输出级模块，用于选择性地为PMOS和NMOS晶体管提供各种栅偏置。 反馈电路耦合在将输出级模块耦合到第二系统的I / O焊盘和用于控制开关模块以响应于I / O焊盘处的电压而产生栅极偏压的开关模块，从而确保电压 PMOS和NMOS晶体管的栅极跨在预定范围内。

公开(公告)号：US20070030039A1

公开(公告)日：2007-02-08

申请号：US11196715

申请日：2005-08-03

申请人： Ker-Min Chen

发明人： Ker-Min Chen

IPC分类号： H03L7/00

CPC分类号： H03K17/223

摘要： A power-on control circuit includes a coupling device coupled to a first voltage supply. A first inverter, coupled between the coupling device and a complementary voltage, has an input node coupled to a second voltage supply with a supply voltage level lower than that of the first voltage supply. A level shifter, coupled between the first voltage supply and the complementary voltage, has a first input node connected to an output node of the first inverter and a second input node coupled to the second voltage supply, for generating the power-on control signal when the first voltage supply is powered up and the second voltage supply is turned off and for disabling the power-on control signal when the second voltage supply is subsequently powered up. The coupling device eliminates a leakage current path from the first voltage supply to the complementary voltage through the first inverter.

摘要翻译： 电源接通控制电路包括耦合到第一电压源的耦合装置。 耦合在耦合器件和互补电压之间的第一反相器具有耦合到第二电压源的输入节点，其电源电压电平低于第一电压源的电源电压电平。 耦合在第一电压源和互补电压之间的电平移位器具有连接到第一反相器的输出节点的第一输入节点和耦合到第二电压源的第二输入节点，用于当产生电源接通控制信号时 第一电源通电并且第二电压供应被关闭，并且当第二电压供应随后通电时禁用上电控制信号。 耦合器件消除了通过第一反相器从第一电压源到互补电压的漏电流路径。

公开(公告)号：US07062740B2

公开(公告)日：2006-06-13

申请号：US10444907

申请日：2003-05-22

申请人： Ker-Min Chen ,  Ming-Hsiang Song ,  Chang-Fen Hu

发明人： Ker-Min Chen ,  Ming-Hsiang Song ,  Chang-Fen Hu

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5068

摘要： A method and system is disclosed for generating a desired input/output (I/O) cell based on a basic cell from a library. After identifying a configuration requirement for a desired I/O cell to be used for an integrated circuit design, at least one basic cell is selected, the basic cell having a base component for generating the desired I/O cell to meet the configuration requirement. A connection template is generated having one or more programmable connection points identified thereon, the programmable connection points identifying locations for making connections to one or more feature components of the basic cell. The selected basic cell and the connection template are combined to generate a design file, wherein the design file corresponds to the desired I/O cell with the predetermined feature components of the basic cell integrated with the basic component to satisfy the configuration requirement. The disclosed method reduces the design cycle-time as well as circuit-library maintenance and update effort.

摘要翻译： 公开了用于基于来自库的基本单元产生期望的输入/输出（I / O）单元的方法和系统。 在识别要用于集成电路设计的所需I / O单元的配置要求之后，选择至少一个基本单元，所述基本单元具有用于产生所需I / O单元的基本组件以满足配置要求。 生成具有在其上识别的一个或多个可编程连接点的连接模板，可编程连接点识别用于进行到基本单元的一个或多个特征部件的连接的位置。 所选择的基本单元和连接模板被组合以生成设计文件，其中设计文件对应于具有与基本组件集成的基本单元的预定特征组件的期望I / O单元以满足配置要求。 所公开的方法减少了设计周期时间以及电路库维护和更新工作。

公开(公告)号：US20050270079A1

公开(公告)日：2005-12-08

申请号：US10859726

申请日：2004-06-03

申请人： Kuo-Ji Chen ,  Tsung-Hsing Yu ,  Ker-Min Chen

发明人： Kuo-Ji Chen ,  Tsung-Hsing Yu ,  Ker-Min Chen

IPC分类号： H03K5/153 ,  H03K19/00 ,  H03K19/0185 ,  H03L5/00

CPC分类号： H03K19/018521 ,  H03K19/0027

摘要： An input buffer for interfacing a high voltage signal received at an input node to a low voltage circuit comprising low voltage devices is provided. The buffer includes a threshold adjustment circuit including an inverter coupled to a threshold adjusted output node. The inverter includes low voltage devices and is coupled between a high supply voltage node and a ground node. The inverter includes a first and second transistors having biasing nodes coupled to a low voltage supply node of the low voltage circuit and coupled to the threshold adjusted output node. The adjustment circuit provides at the threshold adjusted output node an inverted signal corresponding to the high voltage input signal. The buffer also includes a level shifting circuit including low voltage devices and provides a low voltage signal corresponding to the high voltage input signal in response to said inverted signal.

摘要翻译： 提供了一种用于将在输入节点处接收的高电压信号与包括低电压装置的低压电路接口的输入缓冲器。 缓冲器包括阈值调整电路，其包括耦合到阈值调整输出节点的反相器。 逆变器包括低电压器件，并且耦合在高电源节点和接地节点之间。 反相器包括第一和第二晶体管，其具有耦合到低压电路的低电压电源节点并耦合到阈值调整输出节点的偏置节点。 调整电路在阈值调整后的输出节点提供与高电压输入信号相对应的反相信号。 缓冲器还包括电平移动电路，其包括低电压装置，并且响应于所述反相信号提供对应于高电压输入信号的低电压信号。

公开(公告)号：US06479845B2

公开(公告)日：2002-11-12

申请号：US09946984

申请日：2001-09-06

申请人： Ker-Min Chen

发明人： Ker-Min Chen

IPC分类号： H01L27118

CPC分类号： H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of routing power supply voltage electrodes and reference voltage electrodes which makes efficient use of chip area, maximizes decoupling capacitance, and reduces voltage drops due to electrode resistance is described. The two top wiring layers of an integrated circuit chip are used as power distribution layers to distribute the power supply voltage and reference voltage so that the power supply voltage bus electrode and reference voltage bus electrode are in separate wiring layers. The chip is partitioned into a number of sub-blocks with spaces between the sub-blocks. In a first wiring layer the power supply voltage bus electrode is routed so as to surround each of the sub-blocks. In a second wiring layer the reference voltage bus electrode is routed so as to surround each of the sub-blocks. Distribution electrodes for both the power supply voltage and reference voltage are located in both the first wiring layer and the second wiring layer and distribute the power supply voltage and reference voltage to each of the sub-blocks. Vias are used to connect distribution electrodes on one level to the same voltage distribution electrodes on the other level and to either the main bus for the power supply or the main bus for the reference voltage.

摘要翻译： 描述了使电源电压电极和参考电压电极布线的方法，其有效地利用芯片面积，使去耦电容最大化并且减少由于电极电阻引起的电压降。 集成电路芯片的两个顶部布线层用作配电层，以分配电源电压和参考电压，使得电源电压总线电极和参考电压总线电极处于分离的布线层中。 芯片被划分为多个子块之间的子块之间的空格。 在第一布线层中，电源电压总线电极被布线以围绕每个子块。 在第二布线层中，参考电压总线电极被布线以围绕每个子块。 用于电源电压和参考电压的分配电极都位于第一布线层和第二布线层中，并将电源电压和参考电压分配给每个子块。 通孔用于将一个电平的分配电极连接到另一个电平上的相同电压分配电极，以及用于电源的主总线或用于参考电压的主总线。

公开(公告)号：US06306745B1

公开(公告)日：2001-10-23

申请号：US09666318

申请日：2000-09-21

申请人： Ker-Min Chen

发明人： Ker-Min Chen

IPC分类号： H01L2144

CPC分类号： H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of routing power supply voltage electrodes and reference voltage electrodes which makes efficient use of chip area, maximizes decoupling capacitance, and reduces voltage drops due to electrode resistance is described. The two top wiring layers of an integrated circuit chip are used as power distribution layers to distribute the power supply voltage and reference voltage so that the power supply voltage bus electrode and reference voltage bus electrode are in separate wiring layers. The chip is partitioned into a number of sub-blocks with spaces between the sub-blocks. In a first wiring layer the power supply voltage bus electrode is routed so as to surround each of the sub-blocks. In a second wiring layer the reference voltage bus electrode is routed so as to surround each of the sub-blocks. Distribution electrodes for both the power supply voltage and reference voltage are located in both the first wiring layer and the second wiring layer and distribute the power supply voltage and reference voltage to each of the sub-blocks. Vias are used to connect distribution electrodes on one level to the same voltage distribution electrodes on the other level and to either the main bus for the power supply or the main bus for the reference voltage.

摘要翻译： 描述了使电源电压电极和参考电压电极布线的方法，其有效地利用芯片面积，使去耦电容最大化并且减少由于电极电阻引起的电压降。 集成电路芯片的两个顶部布线层用作配电层，以分配电源电压和参考电压，使得电源电压总线电极和参考电压总线电极处于分离的布线层中。 芯片被划分为多个子块之间的子块之间的空格。 在第一布线层中，电源电压总线电极被布线以围绕每个子块。 在第二布线层中，参考电压总线电极被布线以围绕每个子块。 用于电源电压和参考电压的分配电极都位于第一布线层和第二布线层中，并将电源电压和参考电压分配给每个子块。 通孔用于将一个电平的分配电极连接到另一个电平上的相同电压分配电极，以及用于电源的主总线或用于参考电压的主总线。

公开(公告)号：US08943453B2

公开(公告)日：2015-01-27

申请号：US12813849

申请日：2010-06-11

申请人： Ker-Min Chen ,  Shien-Po Yang ,  Vincent Merigot

发明人： Ker-Min Chen ,  Shien-Po Yang ,  Vincent Merigot

IPC分类号： G06F17/50 ,  G06F9/445

CPC分类号： G06F17/5081 ,  G06F9/44505 ,  G06F17/504 ,  G06F17/505

摘要： A method of checking an integrated circuit design database includes providing the integrated circuit design stored in a storage media; providing application rules; and providing an instance abstract of instances of libraries and IP(s). Instance-level information is extracted from the integrated circuit design database. An application-rule check is performed against the instance-level information using the information provided in an abstract file.

摘要翻译： 检查集成电路设计数据库的方法包括提供存储在存储介质中的集成电路设计; 提供应用规则; 并提供库和IP实例的实例摘要。 从集成电路设计数据库中提取实例级信息。 使用抽象文件中提供的信息对实例级信息执行应用程序规则检查。