公开(公告)号：US20210237434A1

公开(公告)日：2021-08-05

申请号：US16768541

申请日：2019-07-31

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing NG ,  James Michael GARDNER ,  Scott A. LINN

IPC: B41J2/045

Abstract: A memory circuit for a print component including a plurality of I/O pads, including an analog pad, to connect to a plurality of signal paths which communicate operating signals to the print component. The memory circuit includes a controllable selector connected in line with one of the signal paths via the I/O pads, the selector controllable to disconnect the corresponding signal path to the print component, and a memory component to store memory values associated with the print component. A control circuit, in response to a sequence of operating signals received by the I/O pads representing a memory read, to operate the controllable selector to disconnect the signal path to the print component to block the memory read of the print component, and provide an analog signal to the analog pad to provide an analog electrical value at the analog pad representing stored memory values selected by the memory read.

公开(公告)号：US20210221127A1

公开(公告)日：2021-07-22

申请号：US16767914

申请日：2019-02-06

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： James Michael GARDNER ,  Scott A. LINN ,  Michael W. CUMBIE

IPC: B41J2/045

Abstract: A print component includes a plurality of data pads, a clock pad to receive an intermittent clock signal, and a plurality of actuator groups each corresponding to a different liquid type and to a different one of the data pads. Each actuator group includes a plurality of configuration functions, an array of fluid actuators, and an array of memory elements including a first portion corresponding to the plurality of configuration functions and a second portion corresponding to the array of fluid actuators. Each time the intermittent clock signal is present on the clock pad, the array of memory elements to serially load a segment of data bits from the corresponding data pad, including loading a first portion of data bits into the first portion of memory elements, and loading a second portion of data bits into the second portion of memory elements.

公开(公告)号：US20210221122A1

公开(公告)日：2021-07-22

申请号：US16768387

申请日：2019-10-25

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Scott A. LINN ,  James Michael GARDNER

IPC: B41J2/045

Abstract: A logic circuitry package for a replaceable print apparatus component includes an interface to communicate with a print apparatus logic circuit and at least one logic circuit. The at least one logic circuit is configured to receive, via the interface, a request to turn on a clock generator of the logic circuitry package. The at least one logic circuit is configured to receive, via the interface, a request selecting an internal clock signal to sample. The at least one logic circuit is configured to receive, via the interface, a reference clock signal. The at least one logic circuit is configured to transmit, via the interface, a digital value indicating a count of cycles of the selected internal clock signal during a predetermined number of cycles of the reference clock signal.

公开(公告)号：US20210221121A1

公开(公告)日：2021-07-22

申请号：US16768321

申请日：2019-10-25

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Scott A. LINN ,  Michael W. CUMBIE ,  James Michael GARDNER

IPC: B41J2/045

Abstract: A logic circuitry package for a replaceable print apparatus component includes an I2C interface to communicate with a print apparatus logic circuit and at least one logic circuit. The at least one logic circuit is configured to respond to communications over the I2C interface that are directed to an initial or reconfigured I2C address. The at least one logic circuit is configured to receive, via the I2C interface, a write command to a first memory address of the logic circuit to initiate a first function of the logic circuit. The at least one logic circuit is configured to generate first data in response to the first function. The at least one logic circuit is configured to receive, via the I2C interface, a first read command to a second memory address of the logic circuit. The at least one logic circuit is configured to transmit, via the I2C interface, the first data in response to the first read command to the second memory address.

公开(公告)号：US20210213751A1

公开(公告)日：2021-07-15

申请号：US16768649

申请日：2019-10-25

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： James Michael GARDNER ,  Scott A. LINN

IPC: B41J2/175 ,  B41J2/045

Abstract: A logic circuitry package for a replaceable print apparatus component includes an interface to communicate with a print apparatus logic circuit and at least one logic circuit. The at least one logic circuit includes a memory storing at least one temperature calculation parameter. The at least one logic circuit is configured to receive, via the interface, a first request to read the at least one temperature calculation parameter; and transmit, via the interface, the at least one temperature calculation parameter in response to the first request. The at least one logic circuit is configured to receive, via the interface, a second request corresponding to a sensor ID; and transmit, via the interface, a digital value in response to the second request. The digital value adjusted based on the at least one temperature calculation parameter corresponds to an absolute temperature of the print apparatus component.

公开(公告)号：US20210213732A1

公开(公告)日：2021-07-15

申请号：US16956331

申请日：2019-02-06

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： James Michael GARDNER ,  Scott A. LINN ,  Michael W. CUMBIE

IPC: B41J2/045

Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes an interface, a first sensor, a second sensor, and control logic. The interface is to connect to a single contact pad of a host print apparatus. The first sensor is of a first type and is coupled to the interface. The second sensor is of a second type and is coupled to the interface. The second type is different from the first type. The control logic enables the first sensor or the second sensor to provide an enabled sensor. A voltage bias or a current bias applied to the interface generates a sensed current or a sensed voltage, respectively, on the interface indicating the state of the enabled sensor.

公开(公告)号：US20210078334A1

公开(公告)日：2021-03-18

申请号：US16772997

申请日：2019-04-05

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： James Michael GARDNER ,  Sirena Chi LU ,  Scott A. LINN ,  Stephen D. PANSHIN ,  David Owen ROETHIG ,  David N. OLSEN ,  Anthony D. STUDER ,  Michael W. CUMBIE ,  Jefferson P. WARD

IPC: B41J2/175 ,  G06F13/42 ,  G06F21/44 ,  G06F9/30 ,  G06F21/62 ,  H04L9/08 ,  H04L9/32

Abstract: In an example, a method includes, by logic circuitry associated with a replaceable print apparatus component installed in a print apparatus, responding to a sensor data request received from the print apparatus by returning a first response; receiving a calibration parameter from the print apparatus; and returning a second response which is different from the first response.

公开(公告)号：US20210053353A1

公开(公告)日：2021-02-25

申请号：US16965825

申请日：2019-04-05

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： James Michael GARDNER ,  Scott A. LINN ,  Jefferson P. WARD ,  David N. OLSEN ,  Anthony D. STUDER ,  Michael W. CUMBIE ,  Sirena Chi LU

IPC: B41J2/175 ,  G06F13/42 ,  G06F21/44 ,  G03G15/08 ,  B33Y50/00 ,  G06K15/10 ,  G06K15/00

Abstract: A sensor circuit for a replaceable print apparatus component comprises an interface to transmit signals with respect to a print apparatus logic circuit, and further comprises, connected to the interface, at least two sensor cell arrays, each array including nominally the same cells, the cells of one array being nominally different than the cells of the other array, and at least one single cell sensor that is nominally different than the other cells.

公开(公告)号：US20190255837A1

公开(公告)日：2019-08-22

申请号：US16317883

申请日：2016-10-24

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Daryl E ANDERSON ,  Eric MARTIN ,  James Michael GARDNER

IPC: B41J2/045 ,  B41J2/14

Abstract: Example implementations relate to low voltage bias of nozzle sensors. For example, a fluid ejection die according to the present disclosure may include a plurality of nozzles, and each nozzle may include a nozzle sensor and a fluid ejector, among other components. The fluid ejection die may also include a voltage reduction device to maintain a low voltage bias on the plurality of nozzle sensors during an operation of the plurality of nozzles. A plurality of sense circuits may be electrically coupled to a respective nozzle sensor among the plurality of nozzle sensors, and each sense circuit may evaluate a status of the respective nozzle after the operation.