公开(公告)号：US20170358352A1

公开(公告)日：2017-12-14

申请号：US15535765

申请日：2014-12-15

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Ning Ge ,  Jianhua Yang ,  John Paul Strachan ,  Miao Hu

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G06G7/16 ,  G11C13/0007 ,  G11C13/004 ,  G11C2213/79

Abstract: Provided in one example is a nonvolatile memory cross-bar array. The array includes: a number of junctions formed by a number of row lines intersecting a number of column lines; a first set of controls at a first set of the junctions coupling between a first set of the row lines and a first set of the column lines; a second set of controls at a second set of the junctions coupling between a second set of the row lines and a second set of the column lines; and a current collection line to collect currents from the controls of the first set and the second set through their respective column lines and output a result current corresponding to a sum of a first dot product and a second dot product.

公开(公告)号：US09793473B2

公开(公告)日：2017-10-17

申请号：US14914808

申请日：2013-09-05

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Shih-Yuan Wang ,  Jianhua Yang ,  Minxian Max Zhang ,  Alexandre M. Bratkovski ,  R. Stanley Williams

IPC: H01L47/00 ,  H01L45/00

CPC classification number: H01L45/1253 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148 ,  H01L45/1608

Abstract: A memristor structure may be provided that includes a first electrode, a second electrode, and a buffer layer disposed on the first electrode. The memristor structure may include a switching layer interposed between the second electrode and the buffer layer to form, when a voltage is applied, a filament or path that extends from the second electrode to the buffer layer and to form a Schottky-like contact or a heterojunction between the filament and the buffer layer.

公开(公告)号：US20170271589A1

公开(公告)日：2017-09-21

申请号：US15329801

申请日：2015-01-26

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Minxian Max Zhang ,  Jianhua Yang ,  Zhiyong Li ,  R. Stanley Williams

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/146 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/1633 ,  H01L45/1641

Abstract: A resistive memory array includes a plurality of resistive memory devices. A sneak path current in the resistive memory array is reduced when a negative temperature coefficient of resistance material is incorporated in series with a negative differential resistance selector that is in series with a memristor switching material at a junction formed at a cross-point between two conductors of one of the plurality of resistive memory devices.

公开(公告)号：US20170271009A1

公开(公告)日：2017-09-21

申请号：US15329845

申请日：2015-01-28

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Jianhua Yang ,  Ning Ge ,  John Paul Strachan ,  Gary Gibson ,  Warren Jackson

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/004 ,  G11C2213/73 ,  G11C2213/74 ,  G11C2213/76

Abstract: In one example, a volatile selector is switched from a low conduction state to a first high conduction state with a first voltage level and then the first voltage level is removed to activate a relaxation time for the volatile selector. The relaxation time is defined as the time the first volatile selector transitions from the high conduction state back to the low conduction state. The volatile selector is switched with a second voltage level of opposite polarity to the first voltage level to significantly reduce the relaxation time of the volatile selector.