公开(公告)号：US20070049015A1

公开(公告)日：2007-03-01

申请号：US11219303

申请日：2005-09-01

Applicant: Hasan Nejad ,  Thomas Figura ,  Gordon Haller ,  Ravi Iyer ,  John Meldrim ,  Justin Harnish

Inventor： Hasan Nejad ,  Thomas Figura ,  Gordon Haller ,  Ravi Iyer ,  John Meldrim ,  Justin Harnish

IPC: H01L21/4763

CPC classification number: H01L21/823835 ,  H01L21/28097 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823814 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10897 ,  H01L29/4975 ,  H01L29/66621 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.

Abstract translation: 为嵌入硅完全硅化提供了方法和结构。 在沟槽内提供硅。 在硅上提供了一种金属混合物，其中一种金属在硅中比硅中更容易扩散到金属中，而另一种金属在硅中比在金属中的硅更容易扩散。 示例性的混合物包括80％的镍和20％的钴。 尽管沟槽的纵横比相对较高，但沟槽内的硅可以完全无硅化物形成。 在其他设备中，可以通过用于存储器阵列的方法形成凹陷接入设备（RAD）。

公开(公告)号：US20050226041A1

公开(公告)日：2005-10-13

申请号：US11150349

申请日：2005-06-13

Applicant: Hasan Nejad ,  Mirmajid Seyyedy

Inventor： Hasan Nejad ,  Mirmajid Seyyedy

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/22 ,  H01L27/24 ,  G11C11/00

CPC classification number: H01L27/228 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/16 ,  G11C13/004 ,  G11C2013/0054 ,  H01L27/2481

Abstract: This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple memory cells, which can be stacked vertically above one another in a plurality of memory array layers arranged in a “Z” axis direction.

Abstract translation: 本发明涉及存储器技术以及存储器阵列结构的新变化，以便从交叉点和1T-1Cell架构中融入某些优点。 通过组合这些布局的某些特性，可以利用1T-1Cell架构的快速读取时间和更高的信噪比以及交叉点架构的更高的打包密度。 单个访问晶体管16用于读取可以以“Z”轴方向布置的多个存储器阵列层中的彼此垂直堆叠的多个存储单元。

公开(公告)号：US20050226037A1

公开(公告)日：2005-10-13

申请号：US11142447

申请日：2005-06-02

Applicant: Hasan Nejad ,  Mirmajid Seyyedy

Inventor： Hasan Nejad ,  Mirmajid Seyyedy

IPC: G11C11/00 ,  G11C11/16

CPC classification number: H01L27/228 ,  G11C5/02 ,  G11C11/16

Abstract: This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of MRAM cells each column being provided in a respective stacked memory layer.

Abstract translation: 本发明涉及一种在读取操作期间结合来自交叉点和1T-1MTJ架构的某些优点的MRAM阵列体系结构。 通过使用单个访问晶体管来控制1T-1MTJ架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度，以控制每个列的多个堆叠列的MRAM单元的读数 设置在相应的堆叠存储层中。

公开(公告)号：US06940748B2

公开(公告)日：2005-09-06

申请号：US10146113

申请日：2002-05-16

Applicant: Hasan Nejad ,  Mirmajid Seyyedy

Inventor： Hasan Nejad ,  Mirmajid Seyyedy

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/22 ,  G11C11/14

CPC classification number: G11C11/16 ,  B82Y10/00 ,  G11C11/15 ,  H01L27/228

Abstract: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple MRAM cells, which can be stacked vertically above one another a plurality of MRAM array layers arranged in a “Z” axis direction.

Abstract translation: 本发明涉及MRAM技术和MRAM阵列体系结构的新变型，其中包含了来自交叉点和1T-1MTJ架构的某些优点。 通过组合这些布局的某些特性，可以利用1T-1MTJ架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度。 单个访问晶体管16用于读取可以以“Z”轴方向布置的多个MRAM阵列层彼此垂直堆叠的多个MRAM单元。

公开(公告)号：US20050162898A1

公开(公告)日：2005-07-28

申请号：US11081652

申请日：2005-03-17

Applicant: Hasan Nejad ,  Mirmajid Seyyedy

Inventor： Hasan Nejad ,  Mirmajid Seyyedy

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/22 ,  G11C11/00

CPC classification number: G11C11/16 ,  B82Y10/00 ,  G11C11/15 ,  H01L27/228

Abstract: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple MRAM cells, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.

Abstract translation: 本发明涉及MRAM技术和MRAM阵列体系结构的新变型，其中包含了来自交叉点和1T-1MTJ架构的某些优点。 通过组合这些布局的某些特性，可以利用1T-1MTJ架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度。 单个访问晶体管16用于读取多个MRAM单元，其可以在以“Z”轴方向布置的多个MRAM阵列层中彼此垂直堆叠堆叠。

公开(公告)号：US06882566B2

公开(公告)日：2005-04-19

申请号：US10895975

申请日：2004-07-22

Applicant: Hasan Nejad ,  Mirmajid Seyyedy

Inventor： Hasan Nejad ,  Mirmajid Seyyedy

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/22 ,  G11C11/14

CPC classification number: G11C11/16 ,  B82Y10/00 ,  G11C11/15 ,  H01L27/228

Abstract: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple MRAM cells, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.

Abstract translation: 本发明涉及MRAM技术和MRAM阵列体系结构的新变型，其中包含了来自交叉点和1T-1MTJ架构的某些优点。 通过组合这些布局的某些特性，可以利用1T-1MTJ架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度。 单个访问晶体管16用于读取多个MRAM单元，其可以在以“Z”轴方向布置的多个MRAM阵列层中彼此垂直堆叠堆叠。

公开(公告)号：US06828639B2

公开(公告)日：2004-12-07

申请号：US10198194

申请日：2002-07-17

Applicant: Hasan Nejad ,  James G. Deak

Inventor： Hasan Nejad ,  James G. Deak

IPC: H01L2714

CPC classification number: H01L27/222 ,  G11C11/15 ,  H01L43/08 ,  H01L43/12

Abstract: MRAM structures employ the magnetic properties of layered magnetic and non-magnetic materials to read memory storage logic states. Improvements in switching reliability may be achieved by altering the shape of the layered magnetic stack structure. Forming recessed regions with sloped interior walls in an ILD layer prior to depositing the layered magnetic stack structure produces a significant advantage over the prior art by allowing a CMP process to be used to define the magnetic bit shapes. The sloped interior walls of the recessed regions, which is singular to the present invention, provide a unique formation and shaping of the magnetic stack structure, which may reduce the magnetic coupling effect between magnetic layers of the magnetic stack structure.

Abstract translation: MRAM结构采用分层磁性和非磁性材料的磁性来读取存储器存储逻辑状态。 可以通过改变分层磁堆栈结构的形状来实现开关可靠性的改进。 在沉积分层磁堆栈结构之前，在ILD层中形成具有倾斜内壁的凹陷区域通过允许使用CMP工艺来定义磁头形状而产生比现有技术更大的优点。 凹陷区域的倾斜内壁，对于本发明而言是单一的，提供了磁性堆叠结构的独特的形成和成形，这可以减小磁性堆叠结构的磁性层之间的磁耦合效应。