公开(公告)号：US12190118B2

公开(公告)日：2025-01-07

申请号：US18339454

申请日：2023-06-22

Applicant: INTEL CORPORATION

Inventor： Christopher J. Hughes ,  Prasoonkumar Surti ,  Guei-Yuan Lueh ,  Adam T. Lake ,  Jill Boyce ,  Subramaniam Maiyuran ,  Lidong Xu ,  James M. Holland ,  Vasanth Ranganathan ,  Nikos Kaburlasos ,  Altug Koker ,  Abhishek R. Appu

IPC: G06F9/38 ,  G06F9/50 ,  G06F9/54 ,  G06F12/084 ,  G06T1/60

Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.

公开(公告)号：US20240354889A1

公开(公告)日：2024-10-24

申请号：US18759347

申请日：2024-06-28

Applicant: Intel Corporation

Inventor： Jill Boyce ,  Maxym Dmytrychenko

IPC: G06T3/12 ,  G06T3/16 ,  H04N23/698

CPC classification number: G06T3/12 ,  G06T3/16 ,  H04N23/698

Abstract: A mechanism is described for facilitating hemisphere cube map projection format imaging environments, according to one embodiment. A method of embodiments, as described herein, includes capturing, by a camera coupled to one or more processors, an image having image content, wherein the image content being represented by the image is omnidirectional such that the image content is mapped on a sphere while representing less than the sphere; mapping the image to a cubic representation based on six faces of a cube, wherein one or more of the six faces are classified as inactive regions such that they remain unoccupied or partially occupied; and arranging, based on the cubic representation, the six faces in a compact representation by avoiding inclusion of the inactive regions.

公开(公告)号：US20240348806A1

公开(公告)日：2024-10-17

申请号：US18677514

申请日：2024-05-29

Applicant: Intel Corporation

Inventor： Jill Boyce

IPC: H04N19/196 ,  H04N19/136 ,  H04N19/42 ,  H04N19/463 ,  H04N19/70

CPC classification number: H04N19/196 ,  H04N19/136 ,  H04N19/42 ,  H04N19/463 ,  H04N19/70

Abstract: A mechanism is described for facilitating defining of interoperability signaling and conformance points for the PCC standard in computing environments. A computing device of embodiments, as described herein, includes a decoder to decode a compressed bitstream of video data representing a point cloud, point cloud reconstructor circuitry to reconstruct a point cloud from the decoded patch video data, a syntax element parser to receive at least one syntax element representing interoperability signaling in the compressed bitstream to indicate the number of points in one or more pictures of the video data, and processing hardware to determine if the number of points in the one or more pictures of the compressed bitstream is within the conformance limits of the point cloud reconstructor circuitry.

公开(公告)号：US12069302B2

公开(公告)日：2024-08-20

申请号：US17918859

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Jill Boyce ,  Basel Salahieh

IPC: H04N19/597 ,  G06T7/50 ,  G06V10/54 ,  G06V10/74 ,  G06V10/764 ,  H04N19/167 ,  H04N19/182 ,  H04N19/46

CPC classification number: H04N19/597 ,  G06T7/50 ,  G06V10/54 ,  G06V10/761 ,  G06V10/764 ,  H04N19/167 ,  H04N19/182 ,  H04N19/46

Abstract: Methods, apparatus, systems and articles of manufacture for texture based immersive video coding are disclosed. An example apparatus includes a correspondence labeler to (i) identify first unique pixels and first corresponding pixels included in a plurality of pixels of a first view and (ii) identify second unique pixels and second corresponding pixels included in a plurality of pixels of a second view; a correspondence patch packer to (i) compare adjacent pixels in the first view and (ii) identify a first patch of unique pixels and a second patch of corresponding pixels based on the comparison of the adjacent pixels and the correspondence relationships, the second patch of corresponding pixels tagged with a correspondence list identifying corresponding patches in the second view; and an atlas generator to generate at least one atlas to include in encoded video data, the encoded video data not including depth maps.

公开(公告)号：US12063378B2

公开(公告)日：2024-08-13

申请号：US18466590

申请日：2023-09-13

Applicant: Intel Corporation

Inventor： Jill Boyce

IPC: H04N19/196 ,  H04N19/136 ,  H04N19/42 ,  H04N19/463 ,  H04N19/70

CPC classification number: H04N19/196 ,  H04N19/136 ,  H04N19/42 ,  H04N19/463 ,  H04N19/70

Abstract: A mechanism is described for facilitating defining of interoperability signaling and conformance points for the PCC standard in computing environments. A computing device of embodiments, as described herein, includes a decoder to decode a compressed bitstream of video data representing a point cloud, point cloud reconstructor circuitry to reconstruct a point cloud from the decoded patch video data, a syntax element parser to receive at least one syntax element representing interoperability signaling in the compressed bitstream to indicate the number of points in one or more pictures of the video data, and processing hardware to determine if the number of points in the one or more pictures of the compressed bitstream is within the conformance limits of the point cloud reconstructor circuitry.

公开(公告)号：US12047575B2

公开(公告)日：2024-07-23

申请号：US17539099

申请日：2021-11-30

Applicant: Intel Corporation

Inventor： Alexander Alshin ,  Jill Boyce ,  Zhijun Lei ,  Miroslav Goncharenko ,  Vasily Aristarkhov

IPC: H04N19/13 ,  H04N19/176 ,  H04N19/196 ,  H04N19/91

CPC classification number: H04N19/13 ,  H04N19/176 ,  H04N19/196 ,  H04N19/91

Abstract: Methods, apparatus, systems, and articles of manufacture for multi-symbol equiprobable mode entropy coding, An example apparatus includes equiprobabie bypass control circuitry to determine whether an input value associated with the one or more blocks is greater than a reference value. The example apparatus also includes interval control circuitry to, based on the determination, adjust at least one of an upper limit or a lower limit based on an approximate value approximating a product of (1) a quotient of (a) a difference between the alphabet size and one and (b) the alphabet size and (2) the upper limit, the upper limit and the lower limit forming a range of values within which the input value is to be encoded.

公开(公告)号：US20240236337A1

公开(公告)日：2024-07-11

申请号：US18571714

申请日：2021-10-06

Applicant: Intel Corporation

Inventor： Gang Shen ,  Guangxin Xu ,  Jill Boyce

IPC: H04N19/167 ,  H04N13/178 ,  H04N13/194 ,  H04N13/366 ,  H04N19/119 ,  H04N19/172 ,  H04N19/597

CPC classification number: H04N19/167 ,  H04N13/178 ,  H04N13/194 ,  H04N13/366 ,  H04N19/119 ,  H04N19/172 ,  H04N19/597

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to reduce latency during viewport switching in immersive video. An example apparatus include at least one memory, instructions in the apparatus, and processor circuitry to execute the instructions to: obtain a first bitstream having a first encoded frame and a second encoded frame, the second encoded frame encoded at a higher resolution than the first encoded frame and having a coding dependency on the first encoded frame, rewrite the first bitstream into a second bitstream based on field of view information, the second bitstream including a third encoded frame indicative of a portion of the second encoded frame that corresponds to the field of view information and including the first encoded frame, and transmit the second bitstream to a client device for decoding and rendering the portion of the second encoded frame.

公开(公告)号：US20240155094A1

公开(公告)日：2024-05-09

申请号：US18505356

申请日：2023-11-09

Applicant: Intel Corporation

Inventor： Eyal Ruhm ,  Jill Boyce ,  Asaf J. Shenberg

IPC: H04N13/161

CPC classification number: H04N13/161

Abstract: Embodiments are generally directed to selective packing of patches for immersive video. An embodiment of a processing system includes one or more processor cores; and a memory to store data for immersive video, the data including a plurality of patches for multiple projection directions. The system is select the patches for packing, the selection of the patches based at least in part on which of the multiple projection directions is associated with each of the patches. The system is to encode the patches into one or more coded pictures according to the selection of the patches.

公开(公告)号：US11756153B2

公开(公告)日：2023-09-12

申请号：US16415689

申请日：2019-05-17

Applicant: Intel Corporation

Inventor： Jill Boyce ,  Maxym Dmytrychenko

IPC: G06T3/00 ,  H04N23/698

CPC classification number: G06T3/0062 ,  G06T3/0087 ,  H04N23/698

Abstract: A mechanism is described for facilitating hemisphere cube map projection format imaging environments, according to one embodiment. A method of embodiments, as described herein, includes capturing, by a camera coupled to one or more processors, an image having image content, wherein the image content being represented by the image is omnidirectional such that the image content is mapped on a sphere while representing less than the sphere; mapping the image to a cubic representation based on six faces of a cube, wherein one or more of the six faces are classified as inactive regions such that they remain unoccupied or partially occupied; and arranging, based on the cubic representation, the six faces in a compact representation by avoiding inclusion of the inactive regions.

公开(公告)号：US11726793B2

公开(公告)日：2023-08-15

申请号：US17095585

申请日：2020-11-11

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Prasoonkumar Surti ,  Guei-Yuan Lueh ,  Adam T. Lake ,  Jill Boyce ,  Subramaniam Maiyuran ,  Lidong Xu ,  James M. Holland ,  Vasanth Ranganathan ,  Nikos Kaburlasos ,  Altug Koker ,  Abhishek R. Appu

IPC: G06F9/38 ,  G06F12/084 ,  G06T1/60 ,  G06F9/50 ,  G06F9/54

CPC classification number: G06F9/3891 ,  G06F9/5066 ,  G06F9/544 ,  G06F12/084 ,  G06T1/60

Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.