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51.发明授权公开(公告)号：US10963246B2
公开(公告)日：2021-03-30
申请号：US16186387
申请日：2018-11-09
Applicant: Intel Corporation
Inventor： Alexander F. Heinecke , Robert Valentine , Mark J. Charney , Raanan Sade , Menachem Adelman , Zeev Sperber , Amit Gradstein , Simon Rubanovich
Abstract: Disclosed embodiments relate to computing dot products of nibbles in tile operands. In one example, a processor includes decode circuitry to decode a tile dot product instruction having fields for an opcode, a destination identifier to identify a M by N destination matrix, a first source identifier to identify a M by K first source matrix, and a second source identifier to identify a K by N second source matrix, each of the matrices containing doubleword elements, and execution circuitry to execute the decoded instruction to perform a flow K times for each element (m, n) of the specified destination matrix to generate eight products by multiplying each nibble of a doubleword element (M,K) of the specified first source matrix by a corresponding nibble of a doubleword element (K,N) of the specified second source matrix, and to accumulate and saturate the eight products with previous contents of the doubleword element.
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52.发明申请公开(公告)号：US20200341759A1
公开(公告)日：2020-10-29
申请号：US16872865
申请日：2020-05-12
Applicant: Intel Corporation
Inventor： Robert Valentine , Mark Charney , Raanan Sade , Elmoustapha Ould-Ahmed-Vall , Jesus Corbal
IPC: G06F9/30
Abstract: An embodiment of the invention is a processor including execution circuitry to, in response to a decoded instruction, convert a half-precision floating-point value to a single-precision floating-point value and store the single-precision floating-point value in each of the plurality of element locations of a destination register. The processor also includes a decoder and the destination register. The decoder is to decode an instruction to generate the decoded instruction.
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公开(公告)号：US10776190B2
公开(公告)日：2020-09-15
申请号：US16224579
申请日：2018-12-18
Applicant: Intel Corporation
Inventor： Tomer Stark , Ron Gabor , Joseph Nuzman , Raanan Sade , Bryant E. Bigbee
Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.
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54.发明授权公开(公告)号：US10684854B2
公开(公告)日：2020-06-16
申请号：US15824339
申请日：2017-11-28
Applicant: Intel Corporation
Inventor： Robert Valentine , Mark Charney , Raanan Sade , Elmoustapha Ould-Ahmed-Vall , Jesus Corbal
Abstract: An embodiment of the invention is a processor including execution circuitry to, in response to a decoded instruction, convert a half-precision floating-point value to a single-precision floating-point value and store the single-precision floating-point value in each of the plurality of element locations of a destination register. The processor also includes a decoder and the destination register. The decoder is to decode an instruction to generate the decoded instruction.
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55.发明授权公开(公告)号：US10521226B2
公开(公告)日：2019-12-31
申请号：US15941531
申请日：2018-03-30
Applicant: Intel Corporation
Inventor： Raanan Sade , Thierry Pons , Amit Gradstein , Zeev Sperber , Mark J. Charney , Robert Valentine , Eyal Oz-Sinay
Abstract: Disclosed embodiments relate to efficient complex vector multiplication. In one example, an apparatus includes execution circuitry, responsive to an instruction having fields to specify multiplier, multiplicand, and summand complex vectors, to perform two operations: first, to generate a double-even multiplicand by duplicating even elements of the specified multiplicand, and to generate a temporary vector using a fused multiply-add (FMA) circuit having A, B, and C inputs set to the specified multiplier, the double-even multiplicand, and the specified summand, respectively, and second, to generate a double-odd multiplicand by duplicating odd elements of the specified multiplicand, to generate a swapped multiplier by swapping even and odd elements of the specified multiplier, and to generate a result using a second FMA circuit having its even product negated, and having A, B, and C inputs set to the swapped multiplier, the double-odd multiplicand, and the temporary vector, respectively.
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Patent Agency Ranking
56.发明申请公开(公告)号：US20190163474A1
公开(公告)日：2019-05-30
申请号：US15824339
申请日：2017-11-28
Applicant: Intel Corporation
Inventor： Robert Valentine , Mark Charney , Raanan Sade , Elmoustapha Ould-Ahmed-Vall , Jesus Corbal
IPC: G06F9/30
Abstract: An embodiment of the invention is a processor including execution circuitry to, in response to a decoded instruction, convert a half-precision floating-point value to a single-precision floating-point value and store the single-precision floating-point value in each of the plurality of element locations of a destination register. The processor also includes a decoder and the destination register. The decoder is to decode an instruction to generate the decoded instruction.
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公开(公告)号：US20190042541A1
公开(公告)日：2019-02-07
申请号：US15859271
申请日：2017-12-29
Applicant: Intel Corporation
Inventor： Raanan Sade , Simon Rubanovich , Amit Gradstein , Zeev Sperber , Alexander Heinecke , Robert Valentine , Mark J. Charney , Bret Toll , Jesus Corbal , Elmoustapha Ould-Ahmed-Vall , Menachem Adelman
Abstract: Embodiments detailed herein relate to matrix operations. For example, embodiments of instruction support for matrix (tile) dot product operations are detailed. Exemplary instructions including computing a dot product of signed words and accumulating in a quadword data elements of a matrix pair. Additionally, in some instances, non-accumulating quadword data elements of the matrix pair are set to zero.
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58.发明申请公开(公告)号：US20190004958A1
公开(公告)日：2019-01-03
申请号：US15640060
申请日：2017-06-30
Applicant: Intel Corporation
Inventor： Anil Vasudevan , Venkata Krishnan , Andrew J. Herdrich , Ren Wang , Robert G. Blankenship , Vedaraman Geetha , Shrikant M. Shah , Marshall A. Millier , Raanan Sade , Binh Q. Pham , Olivier Serres , Chyi-Chang Miao , Christopher B. Wilkerson
IPC: G06F12/0868 , G06F12/0811 , G06F3/06 , G06F12/0871
Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.
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公开(公告)号：US10162694B2
公开(公告)日：2018-12-25
申请号：US14977354
申请日：2015-12-21
Applicant: Intel Corporation
Inventor： Tomer Stark , Ron Gabor , Joseph Nuzman , Raanan Sade , Bryant E. Bigbee
Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.
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公开(公告)号：US09690640B2
公开(公告)日：2017-06-27
申请号：US14038334
申请日：2013-09-26
Applicant: Intel Corporation
Inventor： Raanan Sade , Ron Gabor , Deep K. Buch , Theodros Yigzaw , Stanislav Shwartsman
CPC classification number: G06F11/073 , G06F11/0793 , G06F11/08
Abstract: Mechanisms for handling multiple data errors that occur simultaneously are provided. A processing device may determine whether multiple data errors occur in memory locations that are within a range of memory locations. If the multiple memory locations are within the range of memory locations, the processing device may continue with a recovery process. If one of the multiple memory locations is outside of the range of memory locations, the processing device may halt the recovery process.
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