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公开(公告)号：US10776190B2
公开(公告)日：2020-09-15
申请号：US16224579
申请日：2018-12-18
Applicant: Intel Corporation
Inventor： Tomer Stark , Ron Gabor , Joseph Nuzman , Raanan Sade , Bryant E. Bigbee
Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.
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公开(公告)号：US10585741B2
公开(公告)日：2020-03-10
申请号：US16123933
申请日：2018-09-06
Applicant: Intel Corporation
Inventor： Tomer Stark , Ady Tal , Ron Gabor
Abstract: Memory corruption detection technologies are described. A processor core of a processor can receive a first pointer produced by a first memory access instruction of an application being executed by the processor. The first pointer includes a first memory address of a first memory object and a third metadata value and the memory address identifies a memory block in the first set of one or more contiguous memory blocks. The processor core compares the third metadata value to the first metadata value and communicates a memory corruption detection message to the application when the third metadata value does not match the first metadata value. The processor core provides the first memory object to the application when the third metadata value matches the first metadata value.
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公开(公告)号：US10162694B2
公开(公告)日：2018-12-25
申请号：US14977354
申请日：2015-12-21
Applicant: Intel Corporation
Inventor： Tomer Stark , Ron Gabor , Joseph Nuzman , Raanan Sade , Bryant E. Bigbee
Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.
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公开(公告)号：US11693785B2
公开(公告)日：2023-07-04
申请号：US16728527
申请日：2019-12-27
Applicant: Intel Corporation
Inventor： Ron Gabor , Enrico Perla , Raanan Sade , Igor Yanover , Tomer Stark , Joseph Nuzman
IPC: G06F12/00 , G06F12/0895 , G06F12/1081 , G06F12/1009 , G06F12/0811 , G06F12/14 , G06F9/30 , G06F11/30
CPC classification number: G06F12/0895 , G06F9/30043 , G06F9/30101 , G06F11/3037 , G06F12/0811 , G06F12/1009 , G06F12/1081 , G06F12/1441 , G06F12/1466 , G06F2212/7207
Abstract: An apparatus and method for tagged memory management. For example, one embodiment of a processor comprises: execution circuitry to execute instructions and process data, at least one instruction to generate a system memory access request having a first address pointer; and address translation circuitry to determine whether to translate the first address pointer with or without metadata processing, wherein if the first address pointer is to be translated with metadata processing, the address translation circuitry to: perform a lookup in a memory metadata table to identify a memory metadata value, determine a pointer metadata value associated with the first address pointer, and compare the memory metadata value with the pointer metadata value, the comparison to generate a validation of the memory access request or a fault condition, wherein if the comparison results in a validation of the memory access request, then accessing a set of one or more address translation tables to translate the first address pointer to a first physical address and to return the first physical address responsive to the memory access request.
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公开(公告)号：US11645135B2
公开(公告)日：2023-05-09
申请号：US17020663
申请日：2020-09-14
Applicant: Intel Corporation
Inventor： Tomer Stark , Ron Gabor , Joseph Nuzman , Raanan Sade , Bryant E. Bigbee
CPC classification number: G06F11/0751 , G06F9/38 , G06F11/073 , G06F12/00 , G06F12/109 , G06F21/60 , G06F12/145 , G06F2212/1032 , G06F2212/1052 , G06F2212/656
Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.
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Patent Agency Ranking
6.发明授权公开(公告)号：US09766968B2
公开(公告)日：2017-09-19
申请号：US14668862
申请日：2015-03-25
Applicant: Intel Corporation
Inventor： Tomer Stark , Ady Tal , Ron Gabor , Joseph Nuzman
CPC classification number: G06F11/079 , G06F11/073 , G06F11/0751 , G06F11/0772 , G06F11/10 , G06F11/1064
Abstract: Memory corruption detection technologies are described. A processor can include a memory to store data from an application, wherein the memory comprises a memory corruption detection (MCD) table. The processor can also include processor core coupled to the memory. The processor core can receive, from an application, a memory access request to access data of one or more contiguous memory blocks in a memory object of the memory. The processor core can also retrieve data stored in the one or more contiguous memory blocks based on the location indicated by the pointer. The processor core can also retrieve, from the MCD table, allocation information associated with the one or more contiguous memory blocks. The processor core can also send, to the application, a fault message when a fault event associated with the retrieved data occurs based on the allocation information.
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公开(公告)号：US20160371139A1
公开(公告)日：2016-12-22
申请号：US14745172
申请日：2015-06-19
Applicant: Intel Corporation
Inventor： Tomer Stark , Ron Gabor , Ady Tal , Joseph Nuzman
CPC classification number: G06F12/1425 , G06F11/073 , G06F11/0751 , G06F11/0766 , G06F11/0772 , G06F11/0787 , G06F11/1666 , G06F12/0238 , G06F2201/80 , G06F2212/1032
Abstract: Memory corruption detection technologies are described. A processing system can include a processor core including a register to store an address of a memory corruption detection (MCD) table. The processor core can receive, from an application, a memory store request to store data in a first portion of a contiguous memory block of the memory object of a memory. The memory store request comprises a first pointer indicating a first location of the first portion in the memory block to store the data. The processor core can retrieve, from the MCD table, a write protection indicator that indicates a first protection mode of the first portion. The processor core can send, to the application, a fault message when a fault event associated with the first portion occurs based on the first protection mode of the first portion.
Abstract translation: 描述了内存损坏检测技术。 处理系统可以包括处理器核心，其包括用于存储存储器破坏检测（MCD）表的地址的寄存器。 处理器核心可以从应用程序接收存储器存储请求，以将数据存储在存储器的存储器对象的连续存储器块的第一部分中。 存储器存储请求包括指示存储器块中的第一部分的第一位置以存储数据的第一指针。 处理器核心可以从MCD表中检索指示第一部分的第一保护模式的写保护指示符。 当基于第一部分的第一保护模式发生与第一部分相关联的故障事件时，处理器核心可以向应用发送故障消息。
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公开(公告)号：US11030030B2
公开(公告)日：2021-06-08
申请号：US16259736
申请日：2019-01-28
Applicant: Intel Corporation
Inventor： Tomer Stark , Ron Gabor , Joseph Nuzman
Abstract: One embodiment provides an apparatus. The apparatus includes a linear address space, metadata logic and enhanced address space layout randomization (ASLR) logic. The linear address space includes a metadata data structure. The metadata logic is to generate a metadata value. The enhanced ASLR logic is to combine the metadata value and a linear address into an address pointer and to store the metadata value to the metadata data structure at a location pointed to by a least a portion of the linear address. The address pointer corresponds to an apparent address in an enhanced address space. A size of the enhanced address space is greater than a size of the linear address space.
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公开(公告)号：US20210141683A1
公开(公告)日：2021-05-13
申请号：US17020663
申请日：2020-09-14
Applicant: Intel Corporation
Inventor： Tomer Stark , Ron Gabor , Joseph Nuzman , Raanan Sade , Bryant E. Bigbee
IPC: G06F11/07 , G06F12/00 , G06F9/38 , G06F12/109 , G06F21/60
Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.
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公开(公告)号：US10191791B2
公开(公告)日：2019-01-29
申请号：US15201443
申请日：2016-07-02
Applicant: Intel Corporation
Inventor： Tomer Stark , Ron Gabor , Joseph Nuzman
Abstract: One embodiment provides an apparatus. The apparatus includes a linear address space, metadata logic and enhanced address space layout randomization (ASLR) logic. The linear address space includes a metadata data structure. The metadata logic is to generate a metadata value. The enhanced ASLR logic is to combine the metadata value and a linear address into an address pointer and to store the metadata value to the metadata data structure at a location pointed to by a least a portion of the linear address. The address pointer corresponds to an apparent address in an enhanced address space. A size of the enhanced address space is greater than a size of the linear address space.
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