公开(公告)号：US09690640B2

公开(公告)日：2017-06-27

申请号：US14038334

申请日：2013-09-26

Applicant: Intel Corporation

Inventor： Raanan Sade ,  Ron Gabor ,  Deep K. Buch ,  Theodros Yigzaw ,  Stanislav Shwartsman

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/08

CPC classification number: G06F11/073 ,  G06F11/0793 ,  G06F11/08

Abstract: Mechanisms for handling multiple data errors that occur simultaneously are provided. A processing device may determine whether multiple data errors occur in memory locations that are within a range of memory locations. If the multiple memory locations are within the range of memory locations, the processing device may continue with a recovery process. If one of the multiple memory locations is outside of the range of memory locations, the processing device may halt the recovery process.

公开(公告)号：US09612930B2

公开(公告)日：2017-04-04

申请号：US14737768

申请日：2015-06-12

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Eric Rasmussen ,  Deep K. Buch ,  Gordon McFadden ,  Kameswar Subramaniam ,  Amy L. Santoni ,  Willard M. Wiseman ,  Bret L. Toll

IPC: G06F11/00 ,  G06F11/263 ,  G06F11/22 ,  G06F11/14

CPC classification number: G06F11/2635 ,  G06F11/1417 ,  G06F11/1433 ,  G06F11/2242 ,  G06F11/2268 ,  G06F11/27

Abstract: In an embodiment, a processor includes at least one core, a power management unit having a first test register including a first field to store a test patch identifier associated with a test patch and a second field to store a test mode indicator to request a core functionality test, and a microcode storage to store microcode to be executed by the at least one core. Responsive to the test patch identifier, the microcode may access a firmware interface table and obtain the test patch from a non-volatile storage according to an address obtained from the firmware interface table. Other embodiments are described and claimed.

公开(公告)号：US20160182186A1

公开(公告)日：2016-06-23

申请号：US14578313

申请日：2014-12-19

Applicant: Intel Corporation

Inventor： Robert P. Adler ,  Geetani R. Edirisooriya ,  Joseph Murray ,  Deep K. Buch

IPC: H04L1/00

CPC classification number: H04L1/0045 ,  H04L1/0063 ,  H04L12/40 ,  H04L12/40045 ,  H04L2001/0094

Abstract: An inbound sideband interface is provided to receive a message over a first sideband link, and parity logic is provided to calculate a parity bit for the message. Further, an outbound sideband interface is provided to forward the message to another device over a second sideband link. The second sideband link includes a plurality of data wires and a parity bit wire. The message is forwarded over at least some of the data wires and the parity bit is sent to the other device over the parity bit wire to correspond with the message.

Abstract translation: 提供入站边带接口以通过第一边带链路接收消息，并且提供奇偶校验逻辑以计算消息的奇偶校验位。 此外，提供出站边带接口以通过第二边带链路将消息转发到另一设备。 第二边带链路包括多条数据线和奇偶位线。 消息通过至少一些数据线转发，并且奇偶校验位通过奇偶校验位线发送到另一设备以对应于消息。

公开(公告)号：US12235720B2

公开(公告)日：2025-02-25

申请号：US18268956

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Rajat Agarwal ,  Hsing-Min Chen ,  Wei P. Chen ,  Wei Wu ,  Jing Ling ,  Kuljit S. Bains ,  Kjersten E. Criss ,  Deep K. Buch ,  Theodros Yigzaw ,  John G. Holm ,  Andrew M. Rudoff ,  Vaibhav Singh ,  Sreenivas Mandava

IPC: G06F11/10

Abstract: A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.

公开(公告)号：US09602237B2

公开(公告)日：2017-03-21

申请号：US14578313

申请日：2014-12-19

Applicant: Intel Corporation

Inventor： Robert P. Adler ,  Geetani R. Edirisooriya ,  Joseph Murray ,  Deep K. Buch

IPC: G06F11/10 ,  H03M13/00 ,  H04L1/00 ,  H04L12/40

CPC classification number: H04L1/0045 ,  H04L1/0063 ,  H04L12/40 ,  H04L12/40045 ,  H04L2001/0094

Abstract: An inbound sideband interface is provided to receive a message over a first sideband link, and parity logic is provided to calculate a parity bit for the message. Further, an outbound sideband interface is provided to forward the message to another device over a second sideband link. The second sideband link includes a plurality of data wires and a parity bit wire. The message is forwarded over at least some of the data wires and the parity bit is sent to the other device over the parity bit wire to correspond with the message.