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公开(公告)号:US07288981B2
公开(公告)日:2007-10-30
申请号:US11275538
申请日:2006-01-12
CPC分类号: H03K19/018521
摘要: A voltage translator circuit and a method for operating the same. The voltage translator circuit includes (a) an input node, an output node, and a ground node; (b) a voltage divider circuit including a first and second resistors coupled in series between the input node and the ground node; (c) a start voltage circuit coupled to a first voltage and to the input node; (d) a transfer circuit coupled to the output node; and (e) a capacitive circuit having a first and second capacitive nodes. The first capacitive node is coupled to the voltage divider circuit. The second capacitive node is coupled (i) to the first voltage via the start voltage circuit, and (ii) to the output node via the transfer circuit. In response to the input node changing towards the first voltage, the start voltage circuit is capable of disconnecting the second capacitive node from the first voltage.
摘要翻译: 电压转换电路及其操作方法。 电压转换器电路包括(a)输入节点,输出节点和接地节点; (b)分压器电路,包括串联耦合在输入节点和接地节点之间的第一和第二电阻器; (c)耦合到第一电压和输入节点的启动电压电路; (d)耦合到所述输出节点的传输电路; 以及(e)具有第一和第二电容性节点的电容电路。 第一电容节点耦合到分压器电路。 第二电容性节点经由起动电压电路与第一电压耦合(i),以及(ii)经由传输电路连接到输出节点。 响应于输入节点向第一电压变化,启动电压电路能够将第二电容性节点与第一电压断开。
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公开(公告)号:US20140028363A1
公开(公告)日:2014-01-30
申请号:US13556237
申请日:2012-07-24
IPC分类号: H03K5/13
CPC分类号: H03K5/13
摘要: A phase rotator based on voltage referencing is disclosed. A voltage signal is generated that is proportional to the phase difference between two input signals. The voltage signal is then used as the upper voltage limit for a digital-to-analog converter (DAC). The DAC is programmable via an input vector to generate a DAC output. The DAC output is used to generate a phase rotated (phase shifted) output, which is at an intermediate phase between the two input signals.
摘要翻译: 公开了一种基于电压参考的相位旋转器。 产生与两个输入信号之间的相位差成比例的电压信号。 然后将电压信号用作数模转换器(DAC)的上限电压。 DAC可通过输入矢量进行编程,以产生DAC输出。 DAC输出用于产生在两个输入信号之间处于中间相位的相位旋转(相移)输出。
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公开(公告)号:US08466722B2
公开(公告)日:2013-06-18
申请号:US13284265
申请日:2011-10-28
IPC分类号: H03L7/00
CPC分类号: H01L27/0266
摘要: A method for startup and operation of an output stage of a transmitter, the output stage comprising a first protection field effect transistor (FET) and a second protection FET includes enabling a startup circuit; providing a first bias voltage to the first protection FET in the output stage and a second bias voltage to the second protection FET stage in the output stage by the startup circuit; disabling the startup circuit and enabling a protection voltage generator; providing the first bias voltage to the first protection FET in the output stage by the protection voltage generator; and providing the second bias voltage to the second protection FET in the output stage by a second bias voltage power supply.
摘要翻译: 一种用于启动和操作发射机的输出级的方法,所述输出级包括第一保护场效应晶体管(FET)和第二保护FET,使能启动电路; 向所述输出级中的所述第一保护FET提供第一偏置电压,以及通过所述启动电路向所述输出级中的所述第二保护FET级提供第二偏置电压; 禁用启动电路并启用保护电压发生器; 通过保护电压发生器向输出级中的第一保护FET提供第一偏置电压; 以及通过第二偏置电压电源在所述输出级中向所述第二保护FET提供所述第二偏置电压。
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公开(公告)号:US08410835B1
公开(公告)日:2013-04-02
申请号:US13342453
申请日:2012-01-03
IPC分类号: H03L7/06
CPC分类号: H03L7/101 , H03L7/0891 , H03L7/093
摘要: Leakage tolerant phase locked loop (PLL) circuit devices and methods of locking phases of output phase signals to a phase of a reference signal using a leakage tolerant PLL circuit device are provided. Embodiments include a PLL circuit device comprising: a primary loop and a secondary correction circuit. The primary loop includes a phase detector, an error controller, a voltage controlled oscillator (VCO), and feedback divider. The secondary correction circuit is configured to generate and provide a secondary error-frequency signal to the error controller. The secondary correction circuit is configured to generate the secondary error-frequency signal in response to detecting a particular edge of a divided VCO output signal. The primary loop is configured to control a frequency adjustment based on at least one of a first error-frequency-increase signal, a first error-frequency-decrease signal, and the secondary error-frequency signal.
摘要翻译: 提供了泄漏容限锁相环(PLL)电路装置以及使用泄漏容限PLL电路装置将输出相位信号的相位锁定到参考信号的相位的方法。 实施例包括PLL电路装置,其包括:主回路和二次校正电路。 主回路包括相位检测器,误差控制器,压控振荡器(VCO)和反馈分压器。 二次校正电路被配置为产生并向误差控制器提供次级错误频率信号。 二次校正电路被配置为响应于检测到分压的VCO输出信号的特定边缘而产生次级错误频率信号。 主回路被配置为基于第一误差频率增大信号,第一误差 - 频率降低信号和次级错误频率信号中的至少一个来控制频率调整。
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公开(公告)号:US07342429B2
公开(公告)日:2008-03-11
申请号:US11325786
申请日:2006-01-05
申请人: John S. Austin , Ram Kelkar , Pradeep Thiagarajan
发明人: John S. Austin , Ram Kelkar , Pradeep Thiagarajan
IPC分类号: H03K3/289
CPC分类号: H03K23/52 , H03K5/04 , H03K5/05 , H03K5/1565 , H03K21/10 , H03K21/38 , H03K23/44 , H03K23/667
摘要: Several latch circuits including a NAND gate stage and combinations of clocked inverter stages and inverter stages are described. A programmable frequency divider including homologue frequency divider circuits using the latch circuits is also described. Also described is a circuit included in the homologue frequency divides and a method for correcting the duty cycle of clock signals generated by the homologue frequency dividers to 50%.
摘要翻译: 描述了包括NAND门级和时钟反相器级和反相器级的组合的多个锁存电路。 还描述了包括使用锁存电路的同步分频器电路的可编程分频器。 还描述了同源分频器中包括的电路和用于校正由同系分频器产生的时钟信号的占空比为50%的方法。
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公开(公告)号:US20060158237A1
公开(公告)日:2006-07-20
申请号:US11374766
申请日:2006-03-14
申请人: John Austin , Ram Kelkar , Pradeep Thiagarajan
发明人: John Austin , Ram Kelkar , Pradeep Thiagarajan
IPC分类号: H03K3/356
CPC分类号: H03K23/667 , H03K5/04 , H03K5/05 , H03K5/1565 , H03K21/10 , H03K21/38 , H03K23/44 , H03K23/52
摘要: A fast latch including: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage, a first input of the clocked inverter stage coupled to the output of the NAND stage and a second input of the clocked inverter stage coupled to the clock signal; a first inverter stage, a first input of the first inverter stage coupled to an output of the clocked inverter and a second input of the first inverter stage coupled to a reset signal; and a second inverter stage, having an output, an input of the second inverter stage coupled to an output of the first inverter stage. The fast latch is suitable for use in frequency divider circuits also described. A homologue of frequency dividers using the fast latch, a unique 3/4 divider and a 2 divider not using the fast latch are also disclosed.
摘要翻译: 一种快速锁存器,包括:适于接收时钟信号和数据输入信号的NAND级; 时钟反相器级,被连接到NAND级的输出的时钟反相级的第一输入和与时钟信号耦合的时钟反相级的第二输入; 第一反相器级,耦合到所述时钟反相器的输出的第一反相器级的第一输入和耦合到复位信号的第一反相器级的第二输入; 以及第二反相器级,具有输出,所述第二反相器级的输入耦合到所述第一反相器级的输出。 快速锁存器适用于还描述的分频器电路。 还公开了使用快速锁存器的分频器的同系物,独特的3/4分频器和不使用快速锁存器的2分频器。
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公开(公告)号:US20060109947A1
公开(公告)日:2006-05-25
申请号:US11325786
申请日:2006-01-05
申请人: John Austin , Ram Kelkar , Pradeep Thiagarajan
发明人: John Austin , Ram Kelkar , Pradeep Thiagarajan
IPC分类号: H03K21/00
CPC分类号: H03K23/52 , H03K5/04 , H03K5/05 , H03K5/1565 , H03K21/10 , H03K21/38 , H03K23/44 , H03K23/667
摘要: Several latch circuits including a NAND gate stage and combinations of clocked inverter stages and inverter stages are described. A programmable frequency divider including homologue frequency divider circuits using the latch circuits is also described. Also described is a circuit included in the homologue frequency divides and a method for correcting the duty cycle of clock signals generated by the homologue frequency dividers to 50%.
摘要翻译: 描述了包括NAND门级和时钟反相器级和反相器级的组合的多个锁存电路。 还描述了包括使用锁存电路的同步分频器电路的可编程分频器。 还描述了同源分频器中包括的电路和用于校正由同系分频器产生的时钟信号的占空比为50%的方法。
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