公开(公告)号：US08373510B2

公开(公告)日：2013-02-12

申请号：US12106399

申请日：2008-04-21

Applicant: Ram Kelkar

Inventor： Ram Kelkar

IPC: H03L7/00

CPC classification number: H03B5/1228 ,  H03B5/1215 ,  H03B5/1265

Abstract: A programmable filter for LC tank voltage controlled oscillator (VCO) and a design structure for a programmable filter for LC tank VCO. The programmable filter includes a proportional control comprising a plurality of capacitance biased by different input voltages and an integral control comprising a filter element with a capacitance C1 and a set of capacitance biased by a voltage output of the filter element.

Abstract translation: 用于LC箱压控振荡器（VCO）的可编程滤波器和用于LC箱VCO的可编程滤波器的设计结构。 可编程滤波器包括比例控制，该比例控制包括由不同输入电压偏置的多个电容，以及包括具有电容C1的滤波器元件和由滤波器元件的电压输出偏置的一组电容的积分控制。

公开(公告)号：US07728687B2

公开(公告)日：2010-06-01

申请号：US11162966

申请日：2005-09-29

Applicant: Ram Kelkar ,  Anjali R. Malladi

Inventor： Ram Kelkar ,  Anjali R. Malladi

IPC: H03B5/12

CPC classification number: H03B5/1228 ,  H03B5/1212 ,  H03B5/1271

Abstract: An oscillation circuit and the method for operating the same. The circuit includes (a) an LC oscillator including an inductor and a variable capacitor; (b) first and second differentially-coupled transistors (i) electrically coupled to the LC oscillator and (ii) configured to provide negative resistance to the LC oscillator; and (c) a first current-injecting circuit (i) electrically coupled to the first differentially-coupled transistor and (ii) configured to inject a first additional electric current into the first differentially-coupled transistor so as to cause the first differentially-coupled transistor to create a first additional negative resistance to the LC oscillator; and (d) a second current-injecting circuit (i) electrically coupled to the second differentially-coupled transistor and (ii) configured to inject a second additional electric current into the second differentially-coupled transistor so as to cause the second differentially-coupled transistor to create a second additional negative resistance to the LC oscillator.

Abstract translation: 振荡电路及其操作方法。 电路包括（a）包括电感器和可变电容器的LC振荡器; （b）电耦合到LC振荡器的第一和第二差分耦合晶体管（i）和（ii）被配置为向LC振荡器提供负电阻; 和（c）电耦合到第一差分耦合晶体管的第一电流注入电路（i）和（ii）被配置为将第一附加电流注入到第一差分耦合晶体管中，以便使第一差分耦合晶体管 晶体管产生对LC振荡器的第一个附加负电阻; 和（d）电耦合到所述第二差分耦合晶体管的第二电流注入电路（i），以及（ii）被配置为向所述第二差分耦合晶体管注入第二附加电流，以使所述第二差分耦合晶体管 晶体管产生第二个额外的负电阻到LC振荡器。

公开(公告)号：US20090261916A1

公开(公告)日：2009-10-22

申请号：US12106399

申请日：2008-04-21

Applicant: Ram Kelkar

Inventor： Ram Kelkar

IPC: H03B5/08 ,  H04B1/10 ,  G06F17/50

CPC classification number: H03B5/1228 ,  H03B5/1215 ,  H03B5/1265

Abstract: A programmable filter for LC tank voltage controlled oscillator (VCO) and a design structure for a programmable filter for LC tank VCO. The programmable filter includes a proportional control comprising a plurality of capacitance biased by different input voltages and an integral control comprising a filter element with a capacitance C1 and a set of capacitance biased by a voltage output of the filter element.

Abstract translation: 用于LC箱压控振荡器（VCO）的可编程滤波器和用于LC箱VCO的可编程滤波器的设计结构。 可编程滤波器包括比例控制，该比例控制包括由不同输入电压偏置的多个电容，以及包括具有电容C1的滤波器元件和由滤波器元件的电压输出偏置的一组电容的积分控制。

公开(公告)号：US07545191B2

公开(公告)日：2009-06-09

申请号：US12103129

申请日：2008-04-15

Applicant: John S. Austin ,  Ram Kelkar ,  Pradeep Thiagarajan

Inventor： John S. Austin ,  Ram Kelkar ,  Pradeep Thiagarajan

IPC: H03K3/017 ,  H03K5/04

CPC classification number: H03K23/667 ,  H03K5/04 ,  H03K5/05 ,  H03K5/1565 ,  H03K21/10 ,  H03K21/38 ,  H03K23/44 ,  H03K23/52

Abstract: A method for dividing a high-frequency signal. The method including: generating, from a first clock signal, a second clock signal, the second clock cycle time greater than the first clock cycle time, an off-time of one cycle of the second clock signal being one first clock cycle time less than an on-time of one cycle of the second clock signal; shifting in time the second clock signal by half of a first clock cycle time to generate a third clock signal, the second clock cycle time equal to the third clock cycle time; performing a logical AND of the second clock signal and the third clock signal to generate a fourth clock signal, the third clock cycle time equal to the fourth clock cycle time, an on-time of one cycle of the fourth clock signal equal to an off-time of one cycle of the fourth clock signal.

Abstract translation: 一种分频高频信号的方法。 该方法包括：从第一时钟信号产生第二时钟信号，第二时钟周期时间大于第一时钟周期时间，第二时钟信号的一个周期的关闭时间是一个第一时钟周期时间小于 第二时钟信号的一个周期的导通时间; 将第二时钟信号的时间偏移到第一时钟周期时间的一半以产生第三时钟信号，第二时钟周期时间等于第三时钟周期时间; 执行第二时钟信号和第三时钟信号的逻辑与以产生第四时钟信号，第三时钟周期时间等于第四时钟周期时间，第四时钟信号的一个周期的导通时间等于关 - 第四个时钟信号的一个周期的时间。

公开(公告)号：US06943608B2

公开(公告)日：2005-09-13

申请号：US10707250

申请日：2003-12-01

Applicant: Ram Kelkar

Inventor： Ram Kelkar

IPC: H03H11/26 ,  H03K3/03 ,  H03K5/00 ,  H03K5/13

CPC classification number: H03H11/26 ,  H03K3/0322 ,  H03K5/133 ,  H03K2005/00026 ,  H03K2005/00234

Abstract: A structure for a delay cell in a Voltage-Controlled Oscillators (VCO) and method for operating the delay cell. The delay cell comprises a latch and an impedance circuit (comprising resistance and capacitance elements). The impedance circuit electrically couples different nodes of the latch, a supply voltage, and ground. By adjusting the resistance of the impedance circuit, the time needed for the latch to switch states in response to the switching of an input coupled to the latch is adjusted accordingly. By choosing the appropriate nodes of the delay cell as input and output nodes of the delay cell, the delay time of the delay cell can be adjusted by adjusting the resistance of the impedance circuit. As a result, the operating frequency range of the VCO can be widened compared with prior art. Similar impedance circuits can be added to the delay cell to expand the operating frequency range of the VCO.

Abstract translation: 用于电压控制振荡器（VCO）中的延迟单元的结构以及用于操作延迟单元的方法。 延迟单元包括锁存器和阻抗电路（包括电阻和电容元件）。 阻抗电路电耦合锁存器的不同节点，电源电压和接地。 通过调整阻抗电路的电阻，相应地调整锁存器响应于耦合到锁存器的输入的切换来切换状态所需的时间。 通过选择延迟单元的适当节点作为延迟单元的输入和输出节点，可以通过调整阻抗电路的电阻来调整延迟单元的延迟时间。 结果，与现有技术相比，可以扩大VCO的工作频率范围。 类似的阻抗电路可以添加到延迟单元以扩大VCO的工作频率范围。

公开(公告)号：US06940324B2

公开(公告)日：2005-09-06

申请号：US10707121

申请日：2003-11-21

Applicant: Ram Kelkar ,  Anjali R. Malladi

Inventor： Ram Kelkar ,  Anjali R. Malladi

IPC: H03L7/06 ,  H03L7/089

CPC classification number: H03L7/0893 ,  H03L7/0898 ,  H03L2207/04

Abstract: A structure and associated method for varying an effective capacitance within a phase lock loop circuit. The phase lock loop circuit comprises a first charge pump circuit, a second charge pump circuit, and a loop filter circuit. The loop filter circuit comprises a filter capacitor with a constant capacitance value. The first charge pump circuit is electrically connected to the loop filter. The first charge pump circuit to controls a flow of current for the loop filter. The loop filter provides a voltage for a voltage controlled oscillator. The second charge pump circuit is electrically connected to the loop filter circuit in parallel with the filter capacitor. The first charge pump circuit and the second charge pump circuit vary an effective capacitance value of the filter capacitor.

Abstract translation: 用于改变锁相环电路内的有效电容的结构和相关方法。 锁相环电路包括第一电荷泵电路，第二电荷泵电路和环路滤波器电路。 环路滤波器电路包括具有恒定电容值的滤波电容器。 第一电荷泵电路电连接到环路滤波器。 第一个电荷泵电路，用于控制环路滤波器的电流。 环路滤波器为压控振荡器提供电压。 第二电荷泵电路与滤波电容器并联地电连接到环路滤波器电路。 第一电荷泵电路和第二电荷泵电路改变滤波电容器的有效电容值。

公开(公告)号：US20050110534A1

公开(公告)日：2005-05-26

申请号：US10707121

申请日：2003-11-21

Applicant: Ram Kelkar ,  Anjali Malladi

Inventor： Ram Kelkar ,  Anjali Malladi

IPC: H03L7/06 ,  H03L7/089

CPC classification number: H03L7/0893 ,  H03L7/0898 ,  H03L2207/04

Abstract: A structure and associated method for varying an effective capacitance within a phase lock loop circuit. The phase lock loop circuit comprises a first charge pump circuit, a second charge pump circuit, and a loop filter circuit. The loop filter circuit comprises a filter capacitor with a constant capacitance value. The first charge pump circuit is electrically connected to the loop filter. The first charge pump circuit to controls a flow of current for the loop filter. The loop filter provides a voltage for a voltage controlled oscillator. The second charge pump circuit is electrically connected to the loop filter circuit in parallel with the filter capacitor. The first charge pump circuit and the second charge pump circuit vary an effective capacitance value of the filter capacitor

Abstract translation: 用于改变锁相环电路内的有效电容的结构和相关方法。 锁相环电路包括第一电荷泵电路，第二电荷泵电路和环路滤波器电路。 环路滤波器电路包括具有恒定电容值的滤波电容器。 第一电荷泵电路电连接到环路滤波器。 第一个电荷泵电路，用于控制环路滤波器的电流。 环路滤波器为压控振荡器提供电压。 第二电荷泵电路与滤波电容器并联地电连接到环路滤波器电路。 第一电荷泵电路和第二电荷泵电路改变滤波电容器的有效电容值

公开(公告)号：US6057719A

公开(公告)日：2000-05-02

申请号：US92412

申请日：1998-06-05

Applicant: John S. Austin ,  Ram Kelkar

Inventor： John S. Austin ,  Ram Kelkar

IPC: H03K23/54 ,  H03K23/66 ,  H03L7/183 ,  H03B19/00

CPC classification number: H03K23/54 ,  H03K23/665 ,  H03L7/183

Abstract: A programmable, self-resetting divider includes a modified Linear Feedback Shift Register (LFSR) counter that starts in an initial state and increments through a count range. The self-resetting divider also includes a reset circuit that detects a pre-selected final state of the modified LFSR counter, provides an output signal in response to the detecting of the final state, and provides a reset signal to the modified LFSR counter in response to the detecting of the final state.

Abstract translation: 可编程的自复位分频器包括一个修改后的线性反馈移位寄存器（LFSR）计数器，该计数器以初始状态启动并递增计数范围。 自复位分配器还包括复位电路，其检测修改的LFSR计数器的预先选择的最终状态，响应于最终状态的检测提供输出信号，并且响应地向修改的LFSR计数器提供复位信号 以检测最终状态。

公开(公告)号：US5828255A

公开(公告)日：1998-10-27

申请号：US749871

申请日：1996-11-15

Applicant: Ram Kelkar ,  Ilya Iosiphovich Novof ,  Stephen Dale Wyatt

Inventor： Ram Kelkar ,  Ilya Iosiphovich Novof ,  Stephen Dale Wyatt

IPC: H03L7/089 ,  H03L7/06

CPC classification number: H03L7/0893 ,  H03L7/0896 ,  H03L7/0898 ,  H03L2207/06

Abstract: Jitter is controlled in a phase locked loop (PLL) adaptively and continuously in real time by a jitter control circuit. The jitter control circuit makes periodic PLL output jitter measurements and causes sequential measurements to be compared. The comparison provides an indication as to whether output jitter is being improved or degraded. Charge pump gains associated with internal parameters and external parameters that adversely affect output jitter are modified in response to the comparisons. If output jitter is adversely affected by an increment or decrement of one of the gain values, then the gain value is moved in the opposite direction. Output jitter is optimized for both gain values. Such optimization occurs during normal circuit operation and is continuous so as to adapt to changing conditions.

Abstract translation: 抖动由抖动控制电路实时自适应地连续控制在锁相环（PLL）中。 抖动控制电路对周期性PLL输出抖动测量进行比较，并进行顺序测量。 该比较提供了输出抖动是否被改善或降级的指示。 与内部参数相关的电荷泵增益和对输出抖动产生不利影响的外部参数进行了比较。 如果输出抖动受增益值之一的递增或递减的不利影响，则增益值以相反的方向移动。 输出抖动针对增益值进行优化。 这种优化在正常的电路运行期间发生并且是连续的，以便适应变化的条件。

公开(公告)号：US5491439A

公开(公告)日：1996-02-13

申请号：US298695

申请日：1994-08-31

Applicant: Ram Kelkar ,  Ilya I Novof ,  Stephen D. Wyatt

Inventor： Ram Kelkar ,  Ilya I Novof ,  Stephen D. Wyatt

IPC: H03D13/00 ,  H03K3/0231 ,  H03L7/089 ,  H03L7/093 ,  H03L7/095 ,  H03L7/10 ,  H03L7/06

CPC classification number: H03L7/095 ,  H03K3/0231 ,  H03L7/0893 ,  H03D13/004 ,  H03L2207/06 ,  H03L7/0896 ,  H03L7/0898 ,  Y10S331/02

Abstract: A phase locked loop circuit includes a phase/frequency detector which uses a divider circuit and feedback from a clock distribution tree to generate INC and DEC pulses which have no "dead zone". A pair of charge pumps receives the INC and DEC pulses. One charge pump is a differential pump and has voltage controlled common mode feedback circuit to maintain a common mode controlled voltage. A differential current is outputted to a loop filter capacitor by this charge pump. The other charge pump is a single-ended output pump which supplies current to a current controlled oscillator which also receives input from a voltage to current converter. The current controlled oscillator includes a variable resistance load which varies inversely with the magnitude of the input current. A jitter control circuit is provided which reduces jitter in the current controlled oscillator output in the locked phase. Also, a lock indicator is provided which is time independent, and provides a lock indication when the loop enters the locked condition.

Abstract translation: 锁相环电路包括相位/频率检测器，该相位/频率检测器使用分频器电路和来自时钟分配树的反馈来产生没有“死区”的INC和DEC脉冲。 一对电荷泵接收INC和DEC脉冲。 一个电荷泵是差分泵，并具有电压控制的共模反馈电路，以保持共模控制电压。 通过该电荷泵将差分电流输出到环路滤波电容器。 另一个电荷泵是一个单端输出泵，它向电流控制振荡器提供电流，该电流控制振荡器也接收电压到电流转换器的输入。 电流控制振荡器包括与输入电流的大小成反比变化的可变电阻负载。 提供了一种抖动控制电路，可减少锁定相中当前受控振荡器输出的抖动。 而且，提供了与时间无关的锁定指示器，并且当环路进入锁定状态时提供锁定指示。