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公开(公告)号：US20210263706A1
公开(公告)日：2021-08-26
申请号：US17179886
申请日：2021-02-19
Applicant: Infineon Technologies AG
Inventor： Andre Roger , Markus Bichl , Dian Tresna Nugraha , Romain Ygnace
Abstract: A radar device is configured to: select a set of operands comprising several operands, determine a common exponent for the operands of the set of operands, normalize the operands based on the common exponent, compress each operand by reducing the resolution of its mantissa, and store the common exponent and the compressed operands in a memory. Also, a vehicle including such radar device and an according method as well as computer program product are provided.
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公开(公告)号：US11099256B2
公开(公告)日：2021-08-24
申请号：US16000979
申请日：2018-06-06
Applicant: Infineon Technologies AG
Inventor： Andre Roger , Christian Schmid , Romain Ygnace
Abstract: A device for processing radar signals is suggested, the device comprising: (i) a memory, which is arranged to store radar data and (ii) an accessor comprising a DMA engine, wherein the accessor is arranged to access data of the memory via the DMA engine, to filter the accessed data, and to forward the filtered data.
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公开(公告)号：US11085994B2
公开(公告)日：2021-08-10
申请号：US16159957
申请日：2018-10-15
Applicant: Infineon Technologies AG
Inventor： Andre Roger , Romain Ygnace
IPC: G01S7/292 , G01S7/03 , G01S7/288 , G01S13/931
Abstract: A radar device including at least three subcircuits, wherein each subcircuit has a cascade input port and a cascade output port and is chained such that the cascade output port of a first subcircuit is connected to the cascade input port of a subsequent subcircuit, the cascade input port of the last subcircuit of the chain is connected to the cascade output port of its preceding subcircuit, and the cascade output port of the last subcircuit of the chain is connectable to an external device, and wherein the at least three subcircuits are configured to conduct a radar computation in a distributed manner such that intermediate results are conveyed towards the last subcircuit of the chain which is configured to combine these results and supply them towards its cascade output port.
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公开(公告)号：US20190146058A1
公开(公告)日：2019-05-16
申请号：US16169159
申请日：2018-10-24
Applicant: Infineon Technologies AG
Inventor： Andre Roger , Markus Bichl , Romain Ygnace
Abstract: A radar device is disclosed including an input DMA module, at least one processing module, and an output DMA module. The input DMA module is arranged to access a memory and supply data from the memory to the at least one processing module, wherein each of the processing modules is arranged to be enabled or disabled. The at least one processing module that is enabled is arranged to process at least a portion of the data supplied by the input DMA module, and the output DMA module is arranged to store the data that are processed by the at least one processing module that is enabled in the memory. Also, a method for processing data by a radar device is provided.
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公开(公告)号：US20190023277A1
公开(公告)日：2019-01-24
申请号：US16041031
申请日：2018-07-20
Applicant: Infineon Technologies AG
Inventor： Andre Roger , Farhan Bin Khalid , Romain Ygnace
IPC: B60W50/00
Abstract: An electronic control unit includes a signal input circuit configured to receive a sensor signal from a radar sensor or from a lidar Sensor and a processing circuit configured to determine a first condition based on a first representation of the sensor signal, and to generate an activation signal in response to the first condition.
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Patent Agency Ranking
公开(公告)号：US20170234968A1
公开(公告)日：2017-08-17
申请号：US15044445
申请日：2016-02-16
Applicant: Infineon Technologies AG
Inventor： Andre Roger , Romain Ygnace
CPC classification number: G01S7/288 , G01S7/2927 , G01S7/354 , G01S13/343 , G01S13/5246 , G01S13/931 , G01S2007/2883 , G01S2007/356
Abstract: Techniques for radar detection based on preacquisition ramps are discussed. One example system comprises transmitter circuitry, receiver circuitry, and one or more processors. The transmitter circuitry can transmit preacquisition ramps and acquisition ramps. The receiver circuitry can receive preacquisition signals and acquisition signals based on interactions between the environment and the preacquisition ramps and acquisition ramps, respectively. The one or more processors can perform preprocessing based on the preacquisition signals to obtain interim results based on one or more of the environment or the system; generate a range Doppler map based at least in part on the acquisition signals; and evaluate the range Doppler map based at least in part on the interim results.
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公开(公告)号：US20170131394A1
公开(公告)日：2017-05-11
申请号：US15342186
申请日：2016-11-03
Applicant: Infineon Technologies AG
Inventor： Andre Roger , Ygnace Romain , Farhan Bin Khalid
CPC classification number: G01S13/343 , G01S7/023 , G01S7/35 , G01S13/931
Abstract: A method for a radar transmitter is described herein. In accordance with one exemplary embodiment, the method includes generating an RF transmit signal composed of at least one sequence of sub-sequent chirp pulses, wherein pseudo-randomly selected chirp pulses are blanked, and radiating the RF transmit signal via at least one antenna as radar signal.
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公开(公告)号：US20160170010A1
公开(公告)日：2016-06-16
申请号：US15052099
申请日：2016-02-24
Applicant: Infineon Technologies AG
Inventor： Romain Ygnace , Andre Roger
IPC: G01S7/02
CPC classification number: G01S7/02 , G01S7/354 , G01S13/02 , G01S13/931 , G01S2007/2883 , G01S2007/356
Abstract: A device for radar applications includes a computing engine, a radar acquisition unit connected to the computing engine, a timer unit connected to the computing engine, a cascade input port, and a cascade output port. The cascade input port is configured to convey an input signal to the computing engine and the cascade output port is configured to convey an output signal from the computing engine. Further, an according system, a radar system, a vehicle with such radar system and a method are provided.
Abstract translation: 用于雷达应用的装置包括计算引擎，连接到计算引擎的雷达获取单元，连接到计算引擎的定时器单元，级联输入端口和级联输出端口。 级联输入端口被配置为将输入信号传送到计算引擎，并且级联输出端口被配置为传送来自计算引擎的输出信号。 此外，提供了一种相关系统，雷达系统，具有这种雷达系统的车辆和方法。
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公开(公告)号：US09279883B2
公开(公告)日：2016-03-08
申请号：US13770260
申请日：2013-02-19
Applicant: Infineon Technologies AG
Inventor： Romain Ygnace , Andre Roger
CPC classification number: G01S7/02 , G01S7/354 , G01S13/02 , G01S13/931 , G01S2007/2883 , G01S2007/356
Abstract: A device for radar applications includes a computing engine, a radar acquisition unit connected to the computing engine, a timer unit connected to the computing engine, a cascade input port, and a cascade output port. The cascade input port is configured to convey an input signal to the computing engine and the cascade output port is configured to convey an output signal from the computing engine. Further, an according system, a radar system, a vehicle with such radar system and a method are provided.
Abstract translation: 用于雷达应用的装置包括计算引擎，连接到计算引擎的雷达获取单元，连接到计算引擎的定时器单元，级联输入端口和级联输出端口。 级联输入端口被配置为将输入信号传送到计算引擎，并且级联输出端口被配置为传送来自计算引擎的输出信号。 此外，提供了一种相关系统，雷达系统，具有这种雷达系统的车辆和方法。
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公开(公告)号：US20150355319A1
公开(公告)日：2015-12-10
申请号：US14296886
申请日：2014-06-05
Applicant: Infineon Technologies AG
Inventor： Andre Roger , Romain Ygnace , David Addison
CPC classification number: G01S13/02 , G01S7/352 , G01S13/343 , G01S13/42 , G01S13/931 , G01S2007/356
Abstract: A device is suggested for processing input data received by several antennas, the device including a processing unit including a buffer and at least one multiplier, wherein the processing unit is configured to calculate a second stage FFT result based on input data received by a first antenna, multiply the second stage FFT result for the first antenna with a first compensation value, and store the result in the buffer. The processing unit is further configured to calculate a second stage FFT result based on input data received by a second antenna, multiply the second stage FFT for the second antenna with a second compensation value, and add the result to the value stored in the buffer.
Abstract translation: 提出了一种用于处理由几个天线接收的输入数据的装置，该装置包括包括缓冲器和至少一个乘法器的处理单元，其中处理单元被配置为基于由第一天线接收的输入数据来计算第二级FFT结果 ，将第一天线的第二级FFT结果乘以第一补偿值，并将结果存储在缓冲器中。 处理单元还被配置为基于由第二天线接收的输入数据来计算第二级FFT结果，将第二天线的第二级FFT乘以第二补偿值，并将结果添加到存储在缓冲器中的值。
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