公开(公告)号：US08804875B1

公开(公告)日：2014-08-12

申请号：US13925080

申请日：2013-06-24

Applicant: Innophase Inc.

Inventor： Yang Xu ,  Sara Munoz Hermoso

IPC: H03D3/18 ,  H04L27/227

CPC classification number: H03D3/007 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03D1/22 ,  H03D5/00 ,  H04L27/227 ,  H04L27/2272 ,  H04L27/389

Abstract: Compressing a variable phase component of a received modulated signal with a second harmonic injection locking oscillator, and generating a delayed phase-compressed signal with a fundamental injection locking oscillator, and combining the phase-compressed signal and the delayed phase-compressed signal to obtain an estimated derivative of the variable phase component, and further processing the estimated derivative to recover data contained within the received modulated signal.

Abstract translation: 用二次谐波注入锁定振荡器压缩接收到的调制信号的可变相位分量，并用基本注入锁定振荡器产生延迟相位压缩信号，并组合相位压缩信号和延迟相位压缩信号以获得 估计的可变相位分量的导数，并且进一步处理估计的导数以恢复包含在接收的调制信号内的数据。

公开(公告)号：US20140023163A1

公开(公告)日：2014-01-23

申请号：US14034426

申请日：2013-09-23

Applicant: Innophase Inc.

Inventor： Yang Xu

IPC: H04L27/227

CPC classification number: H04L27/2272 ,  H04L27/2071 ,  H04L27/22

Abstract: A receiver is described. The receiver includes a first injection-locked oscillator having a first input configured to receive a BPSK signal and a second input configured to receive a first frequency reference. The receiver also includes a second injection-locked oscillator having a third input configured to receive the BPSK signal and a fourth input configured to receive a second frequency reference. Further, the receiver includes a first phase-locked loop coupled with the second input of the first injection-locked oscillator. The first phase-locked loop is configured to generate the first frequency reference. And, a second phase-locked loop is coupled with the fourth input of the second injection-locked oscillator. The second phase-locked loop is configured to generate the second frequency reference.

Abstract translation: 描述接收机。 接收机包括第一注入锁定振荡器，其具有被配置为接收BPSK信号的第一输入和被配置为接收第一频率参考的第二输入。 接收机还包括第二注入锁定振荡器，其具有被配置为接收BPSK信号的第三输入和被配置为接收第二频率参考的第四输入。 此外，接收机包括与第一注入锁定振荡器的第二输入耦合的第一锁相环。 第一锁相环被配置为产生第一频率参考。 并且，第二锁相环与第二注入锁定振荡器的第四输入耦合。 第二锁相环被配置为产生第二频率参考。

公开(公告)号：US20130195224A1

公开(公告)日：2013-08-01

申请号：US13754841

申请日：2013-01-30

Applicant: Innophase Inc.

Inventor： Yang Xu

IPC: H04L27/22

CPC classification number: H04L27/2272 ,  H04L27/2071 ,  H04L27/22

Abstract: A receiver is described. The receiver includes a filter configured to receive a quadrature phase shift keying (“QPSK”) signal. Further, the receiver includes an amplifier coupled with the filter. And, a QPSK decomposition filter is coupled with the amplifier. The QPSK decomposition filter is configured to generate a first BPSK signal based on the QPSK signal and a second BPSK signal based on the QPSK signal.

Abstract translation: 描述接收机。 接收机包括被配置为接收正交相移键控（“QPSK”）信号的滤波器。 此外，接收机包括与滤波器耦合的放大器。 并且，QPSK分解滤波器与放大器耦合。 QPSK分解滤波器被配置为基于QPSK信号和基于QPSK信号的第二BPSK信号生成第一BPSK信号。

公开(公告)号：US20240007264A1

公开(公告)日：2024-01-04

申请号：US18346189

申请日：2023-06-30

Applicant: Innophase, Inc.

Inventor： Claudio Anzil ,  Yang Xu ,  Farhad Zarkeshvari

IPC: H04L7/04 ,  H04L27/36 ,  H04B7/06

CPC classification number: H04L7/04 ,  H04L27/361 ,  H04B7/0691

Abstract: Transceiver array synchronization by receiving a clock signal and at least one synchronization pulse signal at each transceiver IC of a plurality of transceiver integrated circuit (IC) subarrays, wherein each transceiver IC subarray contains a respective set of serially connected transceiver ICs; and synchronizing the transceiver IC with other transceiver ICs of the respective set of serially connected transceiver ICs by resetting a delta-sigma modulator (DSM) circuit to a predetermined state in accordance with the received at least one synchronization pulse signal.

公开(公告)号：US20210007048A1

公开(公告)日：2021-01-07

申请号：US16900650

申请日：2020-06-12

Applicant: Innophase, Inc.

Inventor： Per Konradsson ,  Yang Xu

IPC: H04W52/02 ,  H04W88/08 ,  H04W48/20

Abstract: Selectively enabling an amplitude processing circuit and a phase processing circuit of a wireless station's polar receiver with respect to reception of a beacon signal. Such systems and methods may include sequentially demodulating symbols of the received beacon signal using at least the phase processing circuit to detect a traffic indication signal value in a data payload portion of the received beacon signal. Upon detecting a condition indicating no data traffic for the wireless station, the phase processing circuit may be turned off. The polar receiver may demodulate symbols of the received beacon signal and upon detecting a beacon preamble symbol sequence, shut off the amplitude processing circuit and set the amplitude to a fixed value. The phase processing circuit in conjunction with the fixed amplitude value may be used to demodulate symbols of the beacon signal.

公开(公告)号：US20200295769A1

公开(公告)日：2020-09-17

申请号：US16890771

申请日：2020-06-02

Applicant: Innophase, Inc.

Inventor： Sara Munoz Hermoso ,  Per Konradsson ,  Yang Xu

IPC: H03L7/099 ,  H03B5/12

Abstract: An example method in accordance with some embodiments includes: determining an output frequency control word (FCW) having a plurality of bits, the output FCW being configured to control an oscillator, the oscillator including a plurality of capacitor banks, the plurality of capacitor banks respectively corresponding to the plurality of bits of the output FCW; storing the output FCW in a clocked delay cell; providing an input clock to the clocked delay cell, wherein the input clock is provided to delay the output FCW by an amount of delay; and, in accordance with the input clock, releasing the delayed output FCW from the clocked delay cell, and respectively applying the plurality of bits of the delayed output FCW to the plurality of capacitor banks of the oscillator.

公开(公告)号：US10651876B1

公开(公告)日：2020-05-12

申请号：US16439412

申请日：2019-06-12

Applicant: Innophase, Inc.

Inventor： Roc Berenguer Perez ,  Yang Xu

IPC: H03L7/099 ,  H04B1/04 ,  H03L7/197

Abstract: An example method according to some embodiments includes receiving, from a modulator, a phase-modulated carrier output signal having a carrier center frequency that is a non-integer multiple of a desired carrier center frequency; generating, by an injection-locked ring oscillator (ILRO), a plurality of phases of the phase-modulated carrier output signal at a plurality of outputs of the ILRO; generating a decoupled fractional frequency output signal by sequentially selecting, using a multiplexer, successive outputs of the plurality of outputs corresponding to successive phases of the plurality of phases, the decoupled fractional frequency output signal having a center frequency equal to an integer multiple of the desired carrier center frequency; and generating, based on the decoupled fractional frequency output signal, a desired phase-modulated carrier output signal that is decoupled from the modulator, the desired phase-modulated carrier output signal having a generated carrier center frequency equal to the desired carrier center frequency.

公开(公告)号：US10320403B2

公开(公告)日：2019-06-11

申请号：US15614560

申请日：2017-06-05

Applicant: Innophase Inc.

Inventor： Yang Xu ,  Sara Munoz Hermoso ,  Roc Berenguer Perez

IPC: H04B3/46 ,  H03L7/24 ,  H03D3/00 ,  H04L27/38

Abstract: Wideband polar receivers and method of operation are described. A phase-modulated input signal is received at a polar receiver that includes an injection-locked oscillator. The injection-locked oscillator includes a plurality of injection points. Based on the frequency of the input signal, a particular Nth harmonic is selected, and the input signal is injected at the set of injection points corresponding to the selected Nth harmonic. The injection-locked oscillator generates an oscillator output signal, and the phase of the input signal is determined from the phase of the oscillator output signal. In some embodiments, the oscillator output signal is frequency-multiplied by N, mixed with the input signal, and filtered for use in amplitude detection. The input signal is decoded based on the phase and amplitude information.

公开(公告)号：US20180287646A1

公开(公告)日：2018-10-04

申请号：US15655676

申请日：2017-07-20

Applicant: Innophase, Inc.

Inventor： Yang Xu ,  Sara Munoz Hermoso

IPC: H04B1/16 ,  H04W4/00 ,  H04J1/02 ,  H04L27/06 ,  H04L27/22 ,  H04L27/14 ,  H04L27/38

CPC classification number: H04B1/16 ,  H04B14/008 ,  H04J1/02 ,  H04L27/00 ,  H04L27/06 ,  H04L27/14 ,  H04L27/22 ,  H04L27/233 ,  H04L27/38 ,  H04L27/3845 ,  H04W4/80

Abstract: Circuitry and methods are described for digital signal demodulation. In a configurable receiver, a method includes receiving a radio frequency signal at the configurable receiver, operating the configurable receiver in a first mode, the first mode including providing the radio frequency signal to an amplitude detection circuit to determine an amplitude, providing the radio frequency signal to a phase detection circuit to determine a phase, and providing the amplitude and phase to a coordinate rotation digital computer (CORDIC) logic circuit, and operating the configurable receiver in a low power mode upon receiving an indication to selectively disable the amplitude detection circuit, the low power mode including providing the radio frequency signal to the phase detection circuit to determine the phase, and providing the phase and a predetermined constant value in lieu of the amplitude to the CORDIC logic circuit.

公开(公告)号：US09985638B2

公开(公告)日：2018-05-29

申请号：US15469073

申请日：2017-03-24

Applicant: Innophase, Inc.

Inventor： Yang Xu ,  Fa Dai ,  Dongyi Liao

IPC: H03L7/06 ,  H03L7/099

CPC classification number: H03L7/0992 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03C3/0925 ,  H03C3/0941 ,  H03C3/095

Abstract: A digitally controlled oscillator (DCO) modulation apparatus and method provides a wideband phase-modulated signal output. An exemplary modulator circuit uses an oscillator in a phase-locked loop. The circuit receives a wrapped-phase input signal, unwraps the wrapped-phase input signal to generate an unwrapped-phase signal, and differentiates the unwrapped-phase signal. The wrapped-phase input signal and the differentiated unwrapped-phase signal are both injected into a feedback loop of the modulator circuit. The feedback loop may include a multi-modulus frequency divider with a frequency divisor that is temporarily incremented or decremented to cancel out abrupt phase jumps associated with the wrapped-phase to unwrapped-phase conversion.