公开(公告)号：US11955979B2

公开(公告)日：2024-04-09

申请号：US17835292

申请日：2022-06-08

Applicant: Apple Inc.

Inventor： Reetika K Agarwal ,  Abbas Komijani ,  Hongrui Wang

IPC: H03L7/00 ,  H03C3/09 ,  H03L7/089 ,  H03L7/091 ,  H03L7/099 ,  H03L7/185 ,  H03L7/197 ,  H04L7/033

CPC classification number: H03L7/0891 ,  H03C3/0941 ,  H03L7/091 ,  H03L7/099 ,  H03L7/185 ,  H03L7/1976 ,  H04L7/033

Abstract: An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.

公开(公告)号：US20170371990A1

公开(公告)日：2017-12-28

申请号：US15192278

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Magnus Olov WIKLUND ,  Emanuele LOPELLI ,  Charles WANG

IPC: G06F17/50 ,  H04W88/02 ,  H03L7/093 ,  H03L7/099

CPC classification number: G06F17/5036 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0966 ,  H03C3/0991 ,  H03L7/093 ,  H03L7/0991 ,  H03L2207/12 ,  H03L2207/50 ,  H04W88/02

Abstract: A method of calibrating an All-Digital Phase Locked Loop (ADPLL) includes obtaining a model of the ADPLL and applying an input signal to both the ADPLL and to the model. The ADPLL generates an actual output of the ADPLL, while the model generates a model output. An error between the actual output of the ADPLL and the model output is then sensed. The method also includes generating a calibration value based on the error between the actual output of the ADPLL and the model output, and adjusting a feedforward gain of the ADPLL based on the calibration value.

公开(公告)号：US20170222794A1

公开(公告)日：2017-08-03

申请号：US15493229

申请日：2017-04-21

Applicant: SUNRISE MICRO DEVICES, INC.

Inventor： Mario LAFUENTE ,  Paul Edward GORDAY

IPC: H04L7/033 ,  H04L27/12

CPC classification number: H04L7/033 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958 ,  H03C3/0991 ,  H04L7/0331 ,  H04L27/0014 ,  H04L27/10 ,  H04L27/12 ,  H04L27/127 ,  H04L27/152 ,  H04L27/3411 ,  H04L43/50 ,  H04L2027/0055

Abstract: Various methods provide for trimming the gain in a dual-port phase-locked loop (PLL) of a radio transceiver. Use is made of the radio's demodulator to perform modulation accuracy measurements, thereby reducing the cost and complexity of external test equipment.

公开(公告)号：US20170207906A1

公开(公告)日：2017-07-20

申请号：US14996017

申请日：2016-01-14

Applicant: FRONTIER MICROSYSTEMS LIMITED

Inventor： Mark DAWKINS

IPC: H04L7/033 ,  H04L7/00

CPC classification number: H04L7/0331 ,  H03C3/0916 ,  H03C3/0941 ,  H03C3/0958 ,  H03C3/0975 ,  H03C5/00 ,  H04L7/0091 ,  H04L27/00

Abstract: A two-point phase modulator comprising a phase locked loop, PLL, having a voltage controlled oscillator, VCO, and a feedback path, a first modulation circuit for introducing a first modulation signal into the feedback path, the first modulation circuit generating the first modulation signal using a reference clock signal extracted from the PLL and derived from a first clock, a second modulation circuit for introducing a second modulation input into the VCO, the second modulation circuit generating the second modulation signal using a clock signal generated independently of the reference clock and a synchronizer for aligning the second modulation signal in time with the first clock signal.

公开(公告)号：US20170005853A1

公开(公告)日：2017-01-05

申请号：US15007969

申请日：2016-01-27

Applicant: SUNRISE MICRO DEVICES, INC.

Inventor： Mario LAFUENTE ,  Paul Edward GORDAY

IPC: H04L27/34 ,  H04L12/26 ,  H04L7/033

CPC classification number: H04L7/033 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958 ,  H03C3/0991 ,  H04L7/0331 ,  H04L27/0014 ,  H04L27/10 ,  H04L27/12 ,  H04L27/127 ,  H04L27/152 ,  H04L27/3411 ,  H04L43/50 ,  H04L2027/0055

Abstract: Various methods provide for trimming the gain in a dual-port phase-locked loop (PLL) of a radio transceiver. Use is made of the radio's demodulator to perform modulation accuracy measurements, thereby reducing the cost and complexity of external test equipment.

Abstract translation: 各种方法提供了在无线电收发器的双端口锁相环（PLL）中调整增益。 使用无线电解调器进行调制精度测量，从而降低外部测试设备的成本和复杂性。

公开(公告)号：US20160248430A1

公开(公告)日：2016-08-25

申请号：US14631305

申请日：2015-02-25

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： KHURRAM WAHEED ,  KEVIN B. TRAYLOR

IPC: H03L7/099 ,  H03M3/00 ,  H03M7/16 ,  H03L7/081 ,  H03B5/12

CPC classification number: H03L7/099 ,  H03B5/124 ,  H03B5/1265 ,  H03C3/00 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958 ,  H03C3/0975 ,  H03L7/081 ,  H03L7/197 ,  H03M3/422 ,  H03M7/165

Abstract: An integrated circuit comprises a dual port modulator and a voltage controlled oscillator (VCO). The dual port modulator has a first input for receiving a transmitter modulation signal, a first output for providing a fractional portion of a high port modulation signal, a second output for providing a integer portion of the high port modulation signal, and a third output for providing a low port modulation signal. The VCO is coupled to the dual port modulator and has a first input for receiving the fractional portion of the high port modulation signal, a second input for receiving the integer portion of the high port modulation signal, a third input for receiving a tuning signal based on the low port modulation signal, and a first output for outputting an RF signal. The dual port modulator provides a signed single bit signal for generating the fractional portion of the high port modulation signal.

Abstract translation: 集成电路包括双端口调制器和压控振荡器（VCO）。 双端口调制器具有用于接收发射机调制信号的第一输入端，用于提供高端口调制信号的分数部分的第一输出端，​​用于提供高端口调制信号的整数部分的第二输出端和用于 提供低端口调制信号。 VCO耦合到双端口调制器，并且具有用于接收高端口调制信号的小数部分的第一输入端，用于接收高端口调制信号的整数部分的第二输入端，用于接收调谐信号的第三输入端 在低端口调制信号上，以及第一输出端用于输出RF信号。 双端口调制器提供用于产生高端口调制信号的小数部分的带符号单位信号。

公开(公告)号：US20160238998A1

公开(公告)日：2016-08-18

申请号：US15041202

申请日：2016-02-11

Applicant: NXP B.V.

Inventor： Nenad Pavlovic ,  Vladislav Dyachenko ,  Tarik Saric

IPC: G04F10/00 ,  H03L7/099 ,  H03L7/197 ,  H03M1/38

CPC classification number: G04F10/005 ,  G01S7/02 ,  G01S7/35 ,  G01S13/32 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958 ,  H03L7/085 ,  H03L7/0992 ,  H03L7/1974 ,  H03L7/1976 ,  H03M1/38

Abstract: A time to digital converter (10) is disclosed. The time to digital converter (10) comprises: a synchronisation block (20) configured to output a voltage pulse (110) with duration based on a time difference between a reference oscillating signal (101) and an input oscillating signal (107); a charge pump (41) arranged to receive the voltage pulse (110) and to convert the voltage pulse into a current pulse; an integrator (50) comprising an integrator capacitor (24, 25), the integrator (50) being configured to receive the current pulse (110) and integrate the current pulse (110) as a charge on the integrator capacitor (24, 25), resulting in an integrator output voltage (115); and a successive approximation register (40) configured to determine the integrator output voltage (115) with respect to a reference voltage by adjusting the charge on the integrator capacitor (24, 25) so as to reduce the integrator output voltage (115) to within a least significant bit (D0) of a reference voltage by successive approximation, and configured to output the determined integrator output voltage (115) as a digital signal (125). A phase locked loop comprising the time to digital converter (10) is disclosed.

Abstract translation: 公开了一种数字转换器（10）。 数字转换器（10）的时间包括：同步块（20），被配置为基于参考振荡信号（101）和输入振荡信号（107）之间的时间差输出具有持续时间的电压脉冲（110）; 布置成接收电压脉冲（110）并将电压脉冲转换成电流脉冲的电荷泵（41）; 积分器（50），包括积分器电容器（24,25），所述积分器（50）被配置为接收所述电流脉冲（110）并且将所述电流脉冲（110）作为所述积分器电容器（24,25）上的电荷进行积分， ，导致积分器输出电压（115）; 以及逐次逼近寄存器（40），被配置为通过调整积分电容器（24,25）上的电荷来确定相对于参考电压的积分器输出电压（115），以便将积分器输出电压（115）减小到 通过逐次逼近的参考电压的最低有效位（D0），并且被配置为输出所确定的积分器输出电压（115）作为数字信号（125）。 公开了一种包括时间到数字转换器（10）的锁相环。

公开(公告)号：US08693959B1

公开(公告)日：2014-04-08

申请号：US09621407

申请日：2000-07-21

Applicant: William J. Domino ,  Scott A. Griffith ,  Dmitriy Rozenblit

Inventor： William J. Domino ,  Scott A. Griffith ,  Dmitriy Rozenblit

IPC: H04B1/40

CPC classification number: H03C3/0966 ,  H03C3/0941 ,  H03C3/0958 ,  H03D3/007 ,  H04B1/30 ,  H04B1/408 ,  H04L27/20

Abstract: A system for transmitting and receiving data is provided. The system includes a direct-conversion receiver that receives a signal modulated on a carrier frequency signal. The direct-conversion receiver includes one or more subharmonic local oscillator mixers. A local oscillator is connected to the direct conversion receiver, and generates a signal having a frequency equal to a subharmonic of the carrier frequency signal. A transmitter is connected to the local oscillator, which uses the local oscillator signal to transmit outgoing data.

Abstract translation: 提供了一种用于发送和接收数据的系统。 该系统包括接收在载波频率信号上调制的信号的直接转换接收机。 直接转换接收器包括一个或多个次谐波本地振荡器混频器。 本地振荡器连接到直接转换接收器，并且产生具有等于载波频率信号的次谐波的频率的信号。 发送器连接到本地振荡器，其使用本地振荡器信号来发送输出数据。

公开(公告)号：US08634512B2

公开(公告)日：2014-01-21

申请号：US13023369

申请日：2011-02-08

Applicant: Lai Kan Leung ,  Chiewcharn Narathong

Inventor： Lai Kan Leung ,  Chiewcharn Narathong

IPC: H03D3/24

CPC classification number: H04L27/20 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0975

Abstract: A two point modulation digital phase locked loop circuit is disclosed. The circuit includes a sampling clock input that is switchable between a plurality of frequencies. The circuit also includes a sigma-delta modulator in a feedback path that receives low-pass modulation data. The circuit also includes a voltage-mode digital-to-analog converter (VDAC) that receives high-pass modulation data. The circuit also includes an analog voltage controlled oscillator coupled to the feedback path and the output of the VDAC. The circuit also includes a phase-to-digital converter (PDC) coupled to the feedback path, the sampling clock and a loop filter.

Abstract translation: 公开了一种双点调制数字锁相环电路。 电路包括可在多个频率之间切换的采样时钟输入。 电路还包括接收低通调制数据的反馈路径中的Σ-Δ调制器。 该电路还包括接收高通调制数据的电压模式数模转换器（VDAC）。 该电路还包括耦合到反馈路径和VDAC的输出的模拟压控振荡器。 电路还包括耦合到反馈路径的相对数字转换器（PDC），采样时钟和环路滤波器。

公开(公告)号：US08588338B2

公开(公告)日：2013-11-19

申请号：US13733380

申请日：2013-01-03

Applicant: SiGe Semiconductor (Europe) Limited

Inventor： Jeffrey Wojtiuk

IPC: H04L27/20

CPC classification number: H04L27/34 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958 ,  H03C5/00 ,  H03F3/217 ,  H03F2200/331 ,  H04L27/361

Abstract: A circuit for providing AM/PM modulation is described. The circuit includes a signal generator, which provides two phase modulated (PM) signals used to form two drive signals which are later combined in a constructive/destructive fashion. The combination of the two phase modulated signals form a signal for driving a load. When the load is driven, the resulting signal is AM/PM modulated.

Abstract translation: 描述了用于提供AM / PM调制的电路。 该电路包括信号发生器，其提供用于形成两个驱动信号的两个相位调制（PM）信号，后者以建设性/破坏性方式组合。 两个相位调制信号的组合形成用于驱动负载的信号。 当负载被驱动时，所得到的信号被AM / PM调制。