公开(公告)号：US10521226B2

公开(公告)日：2019-12-31

申请号：US15941531

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Raanan Sade ,  Thierry Pons ,  Amit Gradstein ,  Zeev Sperber ,  Mark J. Charney ,  Robert Valentine ,  Eyal Oz-Sinay

IPC: G06F9/30 ,  G06F17/16 ,  G06F9/38

Abstract: Disclosed embodiments relate to efficient complex vector multiplication. In one example, an apparatus includes execution circuitry, responsive to an instruction having fields to specify multiplier, multiplicand, and summand complex vectors, to perform two operations: first, to generate a double-even multiplicand by duplicating even elements of the specified multiplicand, and to generate a temporary vector using a fused multiply-add (FMA) circuit having A, B, and C inputs set to the specified multiplier, the double-even multiplicand, and the specified summand, respectively, and second, to generate a double-odd multiplicand by duplicating odd elements of the specified multiplicand, to generate a swapped multiplier by swapping even and odd elements of the specified multiplier, and to generate a result using a second FMA circuit having its even product negated, and having A, B, and C inputs set to the swapped multiplier, the double-odd multiplicand, and the temporary vector, respectively.

公开(公告)号：US20190163474A1

公开(公告)日：2019-05-30

申请号：US15824339

申请日：2017-11-28

Applicant: Intel Corporation

Inventor： Robert Valentine ,  Mark Charney ,  Raanan Sade ,  Elmoustapha Ould-Ahmed-Vall ,  Jesus Corbal

IPC: G06F9/30

Abstract: An embodiment of the invention is a processor including execution circuitry to, in response to a decoded instruction, convert a half-precision floating-point value to a single-precision floating-point value and store the single-precision floating-point value in each of the plurality of element locations of a destination register. The processor also includes a decoder and the destination register. The decoder is to decode an instruction to generate the decoded instruction.

公开(公告)号：US20190042541A1

公开(公告)日：2019-02-07

申请号：US15859271

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Raanan Sade ,  Simon Rubanovich ,  Amit Gradstein ,  Zeev Sperber ,  Alexander Heinecke ,  Robert Valentine ,  Mark J. Charney ,  Bret Toll ,  Jesus Corbal ,  Elmoustapha Ould-Ahmed-Vall ,  Menachem Adelman

IPC: G06F17/16 ,  G06F9/30

Abstract: Embodiments detailed herein relate to matrix operations. For example, embodiments of instruction support for matrix (tile) dot product operations are detailed. Exemplary instructions including computing a dot product of signed words and accumulating in a quadword data elements of a matrix pair. Additionally, in some instances, non-accumulating quadword data elements of the matrix pair are set to zero.

公开(公告)号：US20190004958A1

公开(公告)日：2019-01-03

申请号：US15640060

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Venkata Krishnan ,  Andrew J. Herdrich ,  Ren Wang ,  Robert G. Blankenship ,  Vedaraman Geetha ,  Shrikant M. Shah ,  Marshall A. Millier ,  Raanan Sade ,  Binh Q. Pham ,  Olivier Serres ,  Chyi-Chang Miao ,  Christopher B. Wilkerson

IPC: G06F12/0868 ,  G06F12/0811 ,  G06F3/06 ,  G06F12/0871

Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.

公开(公告)号：US10162694B2

公开(公告)日：2018-12-25

申请号：US14977354

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Tomer Stark ,  Ron Gabor ,  Joseph Nuzman ,  Raanan Sade ,  Bryant E. Bigbee

IPC: G06F11/00 ,  G06F11/07 ,  G06F12/00 ,  G06F9/38

Abstract: Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

公开(公告)号：US09690640B2

公开(公告)日：2017-06-27

申请号：US14038334

申请日：2013-09-26

Applicant: Intel Corporation

Inventor： Raanan Sade ,  Ron Gabor ,  Deep K. Buch ,  Theodros Yigzaw ,  Stanislav Shwartsman

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/08

CPC classification number: G06F11/073 ,  G06F11/0793 ,  G06F11/08

Abstract: Mechanisms for handling multiple data errors that occur simultaneously are provided. A processing device may determine whether multiple data errors occur in memory locations that are within a range of memory locations. If the multiple memory locations are within the range of memory locations, the processing device may continue with a recovery process. If one of the multiple memory locations is outside of the range of memory locations, the processing device may halt the recovery process.

公开(公告)号：US11915000B2

公开(公告)日：2024-02-27

申请号：US18160600

申请日：2023-01-27

Applicant: Intel Corporation

Inventor： Ahmad Yasin ,  Raanan Sade ,  Liron Zur ,  Igor Yanover ,  Joseph Nuzman

IPC: G06F9/30 ,  G06F9/54 ,  G06F11/34 ,  G06F11/30

CPC classification number: G06F9/30145 ,  G06F9/30098 ,  G06F9/544 ,  G06F9/546 ,  G06F11/3037 ,  G06F11/348

Abstract: Systems, methods, and apparatuses relating to circuitry to precisely monitor memory store accesses are described. In one embodiment, a system includes a memory, a hardware processor core comprising a decoder to decode an instruction into a decoded instruction, an execution circuit to execute the decoded instruction to produce a resultant, a store buffer, and a retirement circuit to retire the instruction when a store request for the resultant from the execution circuit is queued into the store buffer for storage into the memory, and a performance monitoring circuit to mark the retired instruction for monitoring of post-retirement performance information between being queued in the store buffer and being stored in the memory, enable a store fence after the retired instruction to be inserted that causes previous store requests to complete within the memory, and on detection of completion of the store request for the instruction in the memory, store the post-retirement performance information in storage of the performance monitoring circuit.

公开(公告)号：US11893389B2

公开(公告)日：2024-02-06

申请号：US18190761

申请日：2023-03-27

Applicant: Intel Corporation

Inventor： Alexander F. Heinecke ,  Robert Valentine ,  Mark J. Charney ,  Raanan Sade ,  Menachem Adelman ,  Zeev Sperber ,  Amit Gradstein ,  Simon Rubanovich

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/3016 ,  G06F9/3802

Abstract: Disclosed embodiments relate to computing dot products of nibbles in tile operands. In one example, a processor includes decode circuitry to decode a tile dot product instruction having fields for an opcode, a destination identifier to identify a M by N destination matrix, a first source identifier to identify a M by K first source matrix, and a second source identifier to identify a K by N second source matrix, each of the matrices containing doubleword elements, and execution circuitry to execute the decoded instruction to perform a flow K times for each element (m, n) of the specified destination matrix to generate eight products by multiplying each nibble of a doubleword element (M,K) of the specified first source matrix by a corresponding nibble of a doubleword element (K,N) of the specified second source matrix, and to accumulate and saturate the eight products with previous contents of the doubleword element.

公开(公告)号：US11847452B2

公开(公告)日：2023-12-19

申请号：US17360562

申请日：2021-06-28

Applicant: Intel Corporation

Inventor： Menachem Adelman ,  Robert Valentine ,  Zeev Sperber ,  Mark J. Charney ,  Bret L. Toll ,  Rinat Rappoport ,  Jesus Corbal ,  Dan Baum ,  Alexander F. Heinecke ,  Elmoustapha Ould-Ahmed-Vall ,  Yuri Gebil ,  Raanan Sade

IPC: G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F17/16 ,  G06F7/76 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F7/485 ,  G06F7/4876 ,  G06F7/762 ,  G06F9/3001 ,  G06F9/3016 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30185 ,  G06F9/30196 ,  G06F9/3818 ,  G06F9/3836 ,  G06F17/16 ,  G06F2212/454

Abstract: Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.

公开(公告)号：US11847185B2

公开(公告)日：2023-12-19

申请号：US17485055

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Dan Baum ,  Chen Koren ,  Elmoustapha Ould-Ahmed-Vall ,  Michael Espig ,  Christopher J. Hughes ,  Raanan Sade ,  Robert Valentine ,  Mark J. Charney ,  Alexander F. Heinecke

IPC: G06F17/16 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F17/16 ,  G06F9/3001 ,  G06F9/3016 ,  G06F9/30101 ,  G06F9/3802

Abstract: Disclosed embodiments relate to accelerating multiplication of sparse matrices. In one example, a processor is to fetch and decode an instruction having fields to specify locations of first, second, and third matrices, and an opcode indicating the processor is to multiply and accumulate matching non-zero (NZ) elements of the first and second matrices with corresponding elements of the third matrix, and executing the decoded instruction as per the opcode to generate NZ bitmasks for the first and second matrices, broadcast up to two NZ elements at a time from each row of the first matrix and each column of the second matrix to a processing engine (PE) grid, each PE to multiply and accumulate matching NZ elements of the first and second matrices with corresponding elements of the third matrix. Each PE further to store an NZ element for use in a subsequent multiplications.