公开(公告)号：US06194929B1

公开(公告)日：2001-02-27

申请号：US08883525

申请日：1997-06-25

申请人： Robert J. Drost ,  Jose M. Cruz ,  Robert J. Bosnyak

发明人： Robert J. Drost ,  Jose M. Cruz ,  Robert J. Bosnyak

IPC分类号： H03L706

CPC分类号： H03L7/0812 ,  H03L7/0893 ,  H03L7/0896

摘要： A delay-locked loop includes a phase detection circuit, a charge pump circuit and a phase shift circuit. The phase detection circuit is coupled to receive a first signal and a second signal. The phase detection circuit generates a phase-error output signal indicative of whether the first signal is ahead of or behind the second signal in phase responsive to receiving the first and second signals. The charge pump circuit is coupled to receive a phase-error signal derived from the phase-error output signal. The charge pump circuit generates a plurality of control output signals. Each of the control output signals are based upon the phase-error signal and by at least one signal derived from one other of the control output signals. The phase shift circuit is coupled to receive a plurality of control input signals and a plurality of periodic input signals. The control input signals are derived from the control output signals. Each of the periodic input signals have a different phase. The phase shift circuit applying the control input signals to select from among the periodic input signals to generate a periodic output signal. The periodic output signal being one of the first and second signals.

摘要翻译： 延迟锁定环包括相位检测电路，电荷泵电路和相移电路。 相位检测电路被耦合以接收第一信号和第二信号。 相位检测电路响应于接收到第一和第二信号而产生指示第一信号是否在相位之前或之后的第二信号的相位误差输出信号。 电荷泵电路被耦合以接收从相位误差输出信号导出的相位误差信号。 电荷泵电路产生多个控制输出信号。 每个控制输出信号基于相位误差信号和由控制输出信号中的另一个导出的至少一个信号。 相移电路被耦合以接收多个控制输入信号和多个周期性输入信号。 控制输入​​信号由控制输出信号导出。 每个周期性输入信号具有不同的相位。 相移电路施加控制输入信号以从周期性输入信号中选择以产生周期性输出信号。 周期性输出信号是第一和第二信号之一。

公开(公告)号：US5955911A

公开(公告)日：1999-09-21

申请号：US944141

申请日：1997-10-06

申请人： Robert J. Drost ,  Robert J. Bosnyak ,  Jose M. Cruz

发明人： Robert J. Drost ,  Robert J. Bosnyak ,  Jose M. Cruz

IPC分类号： H03H11/24 ,  H03H11/28 ,  H03K17/62 ,  H03L5/00

CPC分类号： H03H11/28 ,  H03H11/24

摘要： An on-chip resistance to an input current of an input signal includes a parallel transistor resistor and a control circuit for biasing the transistors of the parallel transistor resistor. The parallel transistor resistor includes first and second transistors of first and second types. Each transistor includes first and second current handling terminals and a control terminal. The control terminals are coupled to receive control signals from the control circuit. The first current handling terminals are coupled to provide an input node for receiving an input signal, and the second current handling terminals are coupled to provide an output signal. The control circuit is coupled to provide the first and second control signals for biasing the respective first and second transistors so that a first derivative of a resistance of the parallel transistor resistor in relation to an input-to-output voltage is zero at a selectable operation point.

摘要翻译： 对输入信号的输入电流的片上电阻包括并联晶体管电阻器和用于偏置并联晶体管电阻器的晶体管的控制电路。 并联晶体管电阻器包括第一和第二类型的第一和第二晶体管。 每个晶体管包括第一和第二电流处理终端和控制终端。 控制端子被耦合以从控制电路接收控制信号。 第一当前处理终端被耦合以提供用于接收输入信号的输入节点，并且第二电流处理终端被耦合以提供输出信号。 控制电路被耦合以提供用于偏置相应的第一和第二晶体管的第一和第二控制信号，使得并行晶体管电阻器的电阻相对于输入到输出电压的一阶导数在可选择的操作时为零 点。

公开(公告)号：US5905399A

公开(公告)日：1999-05-18

申请号：US885598

申请日：1997-06-30

申请人： Robert J. Bosnyak ,  Robert J. Drost

发明人： Robert J. Bosnyak ,  Robert J. Drost

IPC分类号： H01L21/8238 ,  G05F1/46 ,  H01L27/092 ,  H03K17/16 ,  H03K19/00

CPC分类号： G05F1/467

摘要： A CMOS integrated circuit regulator for mixed mode integrated circuits reduces digital switching noise through use of a clamped dual source follower circuit and a charge reservoir bypass capacitor. Relatively constant current is provided to the CMOS logic during transitions to minimize switching noise.

摘要翻译： 用于混合模式集成电路的CMOS集成电路调节器通过使用钳位双源继电器电路和电荷储存器旁路电容来降低数字开关噪声。 在转换期间向CMOS逻辑提供相对恒定的电流以最小化开关噪声。

公开(公告)号：US5767699A

公开(公告)日：1998-06-16

申请号：US653788

申请日：1996-05-28

申请人： Robert J. Bosnyak ,  Robert J. Drost ,  David M. Murata

发明人： Robert J. Bosnyak ,  Robert J. Drost ,  David M. Murata

IPC分类号： H04L25/02 ,  H03K19/0185

CPC分类号： H04L25/0272 ,  H04L25/0298 ,  H04L25/028

摘要： A terminating element is connected between the terminating ends of a transmission line pair. A switching mechanism coupled to the originating ends of the transmission line pair steers a constant current through the transmission line pair. In response to input control signals, the switching mechanism steers the constant current in a complementary fashion into one of the lines of the transmission lines pair to creates a differential output voltage across the terminating element. Controlling the differential voltage by manipulating current flow allows for acurate control over V.sub.OH and V.sub.OL levels. Since the terminating element is connected between terminating ends of the transmission line pair, nearly all of the constant current flowing the driver contributes to the differential output voltage, thereby reducing power undesirable power dissipation. Further, the alternating current flow through the transmission line pair creates a virtual ground at the center of the terminating element and thereby allows drivers in accordance with the present invention to obtain twice the output voltage swing of conventional transmission line drivers without requiring additional current. In this manner, a further reduction in power consumption is achieved.

摘要翻译： 终端元件连接在传输线对的终端之间。 耦合到传输线对的起始端的切换机构引导通过传输线对的恒定电流。 响应于输入控制信号，开关机构以互补方式将恒定电流引导到传输线对中的一条线路中，以在端接元件两端产生差分输出电压。 通过操纵电流控制差分电压可以对VOH和VOL电平进行精确的控制。 由于端接元件连接在传输线对的终端之间，所以流过驱动器的几乎所有的恒定电流有助于差分输出电压，从而减少功率不期望的功耗。 此外，通过传输线对的交流电流在终端元件的中心处产生虚拟接地，从而允许根据本发明的驱动器获得传统传输线驱动器的输出电压摆动的两倍而不需要额外的电流。 以这种方式，实现了功率消耗的进一步降低。

公开(公告)号：US5003509A

公开(公告)日：1991-03-26

申请号：US500083

申请日：1990-03-27

申请人： Robert J. Bosnyak

发明人： Robert J. Bosnyak

IPC分类号： G11C11/41 ,  G11C8/16 ,  G11C11/401

CPC分类号： G11C8/16

摘要： A multi-port, BI-CMOS memory cell is disclosed having a CMOS flip-flop, one or more write ports gated by n-channel FETs, and one or more ECL read ports. Bipolar transistors in the read port are resistively interconnected to equalize emitter voltages during write and standby operations and to resistively isolate the emitters during a read operation.

摘要翻译： 公开了具有CMOS触发器，由n沟道FET门控的一个或多个写入端口和一个或多个ECL读取端口的多端口BI-CMOS存储器单元。 读端口中的双极晶体管电阻互连以在写操作和备用操作期间均衡发射极电压，并在读操作期间电阻隔离发射器。

公开(公告)号：US4859874A

公开(公告)日：1989-08-22

申请号：US101210

申请日：1987-09-25

申请人： Robert J. Bosnyak

发明人： Robert J. Bosnyak

IPC分类号： G06F7/00 ,  H03K19/177

CPC分类号： H03K19/17712

摘要： In accordance with the teachings of this invention, a novel PLA row driver circuit is provided which utilizes a minimum number of components, thereby minimizing integrated circuit surface area, and thus reducing cost, and minimizing stray capacitance, thereby increasing speed of operation. Furthermore, in accordance with the teachings of this invention, a circuit is provided which, while utilizing a minimum number of components, provides a first VOL level to the row line during normal operation of the device, and a second, higher VOL level to the row line during programming.