公开(公告)号：US20110080510A1

公开(公告)日：2011-04-07

申请号：US12890214

申请日：2010-09-24

申请人： Toshiyuki Nishihara

发明人： Toshiyuki Nishihara

IPC分类号： H04N5/335

CPC分类号： H04N5/37455 ,  G01J1/44 ,  G01J2001/444 ,  H04N5/32 ,  H04N5/3355 ,  H04N5/3535 ,  H04N5/355 ,  H04N5/357 ,  H04N5/363 ,  H04N5/3742 ,  H04N5/378

摘要： An image sensor includes a plurality of pixels, a plurality of sense circuits, and a count circuit. Each sense circuit is configured to read out electrical signals from at least one pixel associated with the sense circuit in order to generate data representing whether or not photons have been received by the sense circuit. The count circuit is in communication with a sense circuit selected from the plurality of sense circuits. The count circuit is configured to provide integration results for the pixels associated with the sense circuits based on the data received from the sense circuits.

摘要翻译： 图像传感器包括多个像素，多个感测电路和计数电路。 每个感测电路被配置为从与感测电路相关联的至少一个像素读出电信号，以便生成表示光学器件是否已被感测电路接收的数据。 计数电路与从多个感测电路中选择的感测电路通信。 计数电路被配置为基于从感测电路接收的数据来提供与感测电路相关联的像素的积分结果。

公开(公告)号：US20100199029A1

公开(公告)日：2010-08-05

申请号：US12662153

申请日：2010-04-01

申请人： Toshiyuki Nishihara ,  Daisuke Yoshioka

发明人： Toshiyuki Nishihara ,  Daisuke Yoshioka

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F12/08

CPC分类号： G11C16/12 ,  G06F12/0888 ,  G06F12/0893 ,  G06F2212/2022 ,  G06F2212/2024 ,  G11C16/0483 ,  Y02D10/13

摘要： A storage device that includes a flash memory device providing a storage medium, a cache memory for use with the flash memory device, and a control circuit. In the storage device, based on a write command and provided address information, the control circuit selects either the flash memory device or the cache memory as a writing destination of input data.

摘要翻译： 一种存储装置，包括提供存储介质的闪速存储器件，用于闪速存储器件的高速缓存存储器和控制电路。 在存储装置中，基于写命令和提供的地址信息，控制电路选择闪存装置或高速缓冲存储器作为输入数据的写入目的地。

公开(公告)号：US07571282B2

公开(公告)日：2009-08-04

申请号：US11493658

申请日：2006-07-27

申请人： Toshiyuki Nishihara

发明人： Toshiyuki Nishihara

IPC分类号： G06F13/00

CPC分类号： G06F12/0804 ,  G06F12/0893 ,  G06F2212/2022

摘要： A computer system is provided, wherein a storage device having a flash memory as the main medium is given a cache memory with a high hit rate even in a small capacity and less access overheads, high-speed writing to the flash memory is attained, and the number of rewriting is reduced: wherein a processing device, a cache memory and a flash memory for data via the cache memory to be written in response to a request from the processing device are provided; and a line size of an entry to the cache memory is 1/N (note that N is 2 or larger integer) of an actual page size as a writing unit of the flash memory.

摘要翻译： 提供了一种计算机系统，其中具有闪速存储器作为主介质的存储装置即使在小容量中也被赋予具有高命中率的高速缓冲存储器，并且获得更少的存取开销，实现了对闪速存储器的高速写入，以及 提供重写次数：其中，响应于来自处理装置的请求，提供处理装置，高速缓冲存储器和用于经由高速缓冲存储器进行数据写入的快闪存储器; 并且作为闪速存储器的写入单元的实际页大小的行大小为1 / N（注意N为2或更大整数）。

公开(公告)号：US20080177937A1

公开(公告)日：2008-07-24

申请号：US12003889

申请日：2008-01-03

申请人： Toshiyuki Nishihara ,  Kazuyuki Date

发明人： Toshiyuki Nishihara ,  Kazuyuki Date

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  Y02D10/13

摘要： A storage apparatus includes flash memory, second memory for storing an address translation table, and a control section. The flash memory is formed of multiple pages, each having a spare area, and data is stored on a page-by-page basis. The control section has functions of: saving the table to the flash memory; when writing/updating data, storing the user data, recording, in the table, a correspondence between a logical page address and an address of a page in which the data is stored, and storing information for identifying the corresponding logical page address in the spare area of the page; when the apparatus is started, detecting pages to which data was written after the most recent saving of the table; and scanning the spare area of each page detected and reproducing a state of the table as updated after the most recent saving to reconstruct the table.

摘要翻译： 存储装置包括闪存，用于存储地址转换表的第二存储器和控制部分。 闪存由多页构成，每页具有备用区，并且逐页地存储数据。 控制部分具有以下功能：将表保存到闪存中; 在写入/更新数据时，存储用户数据，在表中记录逻辑页面地址和存储数据的页面的地址之间的对应关系，并且将用于识别对应的逻辑页面地址的信息存储在备用 页面的区域; 当设备启动时，在最近保存表格之后检测写入数据的页面; 并且扫描检测到的每个页面的备用区域并且在最近的保存之后更新的表格再现表的状态以重建表格。

公开(公告)号：US20070124531A1

公开(公告)日：2007-05-31

申请号：US11594882

申请日：2006-11-09

申请人： Toshiyuki Nishihara

发明人： Toshiyuki Nishihara

IPC分类号： G06F12/08

CPC分类号： G06F12/1027 ,  G06F12/0246 ,  G06F12/0292

摘要： A storage device that includes: an address table; a cache memory; a flash memory device being a storage medium for user data; and a control circuit that is in charge of access management for the flash memory device. In the storage device, the control circuit makes access to the user data on the flash memory device via an address table, in the address table, with an index of an address value generated from an initial logical address, location information is acquired for the user data on the flash memory device corresponding to the index, and the address table is segmented in its entirety into a plurality of small address tables for every area of the index, and the small address tables being segmentation results are stored in the flash memory device, read as required when the user data is accessed, and expanded on the cache memory with entries of the small address tables.

摘要翻译： 一种存储设备，包括：地址表; 高速缓冲存储器 闪存设备，用于用户数据的存储介质; 以及负责闪存装置的访问管理的控制电路。 在存储装置中，控制电路通过地址表中的地址表，利用从初始逻辑地址生成的地址值的索引来访问闪存设备上的用户数据，为用户获取位置信息 与索引相对应的闪存设备上的数据，并且地址表被整体分割成索引的每个区域的多个小地址表，并且作为分段结果的小地址表被存储在闪存设备中， 在访问用户数据时根据需要进行读取，并在缓存中扩展小地址表的条目。

公开(公告)号：US20070028034A1

公开(公告)日：2007-02-01

申请号：US11493658

申请日：2006-07-27

申请人： Toshiyuki Nishihara

发明人： Toshiyuki Nishihara

IPC分类号： G06F12/00

CPC分类号： G06F12/0804 ,  G06F12/0893 ,  G06F2212/2022

摘要： A computer system is provided, wherein a storage device having a flash memory as the main medium is given a cache memory with a high hit rate even in a small capacity and less access overheads, high-speed writing to the flash memory is attained, and the number of rewriting is reduced: wherein a processing device, a cache memory and a flash memory for data via the cache memory to be written in response to a request from the processing device are provided; and a line size of an entry to the cache memory is 1/N (note that N is 2 or larger integer) of an actual page size as a writing unit of the flash memory.

摘要翻译： 提供了一种计算机系统，其中具有闪速存储器作为主介质的存储装置即使在小容量中也被赋予具有高命中率的高速缓冲存储器，并且获得更少的存取开销，实现了对闪速存储器的高速写入，以及 提供重写次数：其中，响应于来自处理装置的请求，提供处理装置，高速缓冲存储器和用于经由高速缓冲存储器进行数据写入的快闪存储器; 并且作为闪速存储器的写入单元的实际页大小的行大小为1 / N（注意N为2或更大整数）。

公开(公告)号：US07130208B2

公开(公告)日：2006-10-31

申请号：US11055129

申请日：2005-02-10

申请人： Toshiyuki Nishihara

发明人： Toshiyuki Nishihara

IPC分类号： G11C5/06

CPC分类号： H01L27/11502 ,  G11C11/22

摘要： A ferroelectric-type nonvolatile semiconductor memory comprising a plurality of bit lines and a plurality of memory cells, each memory cell comprising a first electrode, a ferroelectric layer formed at least on said first electrode and a second electrode formed on said ferroelectric layer, a plurality of the memory cells belonging to one of two or more thermal history groups having different thermal histories with regard to their production processes, data of 1 bit being to be stored in one of memory cells forming a pair, another data of 1 bit being to be stored in the other of said memory cells, a pair of said memory cells being connected to a pair of the bit lines, a pair of the bit lines being connected to a differential sense amplifier, wherein, when data stored in one of said memory cells forming a pair is read out, a reference potential is provided to the bit line connected to the other of said memory cells, when another data stored in the other of said memory cells is read out, a reference potential is provided to the bit line connected to the one of said memory cells, and a reference potential of the same level is provided to the bit lines connected to the memory cells belonging to the same thermal history group, and reference potentials of different levels are provided to the bit lines connected to the memory cells belonging to the different thermal history groups.

公开(公告)号：US07009867B2

公开(公告)日：2006-03-07

申请号：US11119227

申请日：2005-04-29

申请人： Toshiyuki Nishihara

发明人： Toshiyuki Nishihara

IPC分类号： G11C11/22

CPC分类号： H01L27/11502 ,  G11C11/22

摘要： A ferroelectric-type nonvolatile semiconductor memory comprising a plurality of bit lines and a plurality of memory cells, each memory cell comprising a first electrode, a ferroelectric layer formed at least on said first electrode and a second electrode formed on said ferroelectric layer, a plurality of the memory cells belonging to one of two or more thermal history groups having different thermal histories with regard to their production processes, data of 1 bit being to be stored in one of memory cells forming a pair, another data of 1 bit being to be stored in the other of said memory cells, a pair of said memory cells being connected to a pair of the bit lines, a pair of the bit lines being connected to a differential sense amplifier, wherein, when data stored in one of said memory cells forming a pair is read out, a reference potential is provided to the bit line connected to the other of said memory cells, when another data stored in the other of said memory cells is read out, a reference potential is provided to the bit line connected to the one of said memory cells, and a reference potential of the same level is provided to the bit lines connected to the memory cells belonging to the same thermal history group, and reference potentials of different levels are provided to the bit lines connected to the memory cells belonging to the different thermal history groups.

公开(公告)号：US06992914B2

公开(公告)日：2006-01-31

申请号：US11106387

申请日：2005-04-13

申请人： Toshiyuki Nishihara

发明人： Toshiyuki Nishihara

IPC分类号： G11C7/00

CPC分类号： H01L27/11502 ,  G11C11/22

摘要： A ferroelectric-type nonvolatile semiconductor memory comprising a plurality of bit lines and a plurality of memory cells, each memory cell comprising a first electrode, a ferroelectric layer formed at least on said first electrode and a second electrode formed on said ferroelectric layer, a plurality of the memory cells belonging to one of two or more thermal history groups having different thermal histories with regard to their production processes, data of 1 bit being to be stored in one of memory cells forming a pair, another data of 1 bit being to be stored in the other of said memory cells, a pair of said memory cells being connected to a pair of the bit lines, a pair of the bit lines being connected to a differential sense amplifier, wherein, when data stored in one of said memory cells forming a pair is read out, a reference potential is provided to the bit line connected to the other of said memory cells, when another data stored in the other of said memory cells is read out, a reference potential is provided to the bit line connected to the one of said memory cells, and a reference potential of the same level is provided to the bit lines connected to the memory cells belonging to the same thermal history group, and reference potentials of different levels are provided to the bit lines connected to the memory cells belonging to the different thermal history groups.

公开(公告)号：US06934175B2

公开(公告)日：2005-08-23

申请号：US10793349

申请日：2004-03-03

申请人： Toshiyuki Nishihara

发明人： Toshiyuki Nishihara

IPC分类号： G11C11/22 ,  H01L21/8246 ,  H01L27/105

CPC分类号： H01L27/11502 ,  G11C11/22

摘要： A ferroelectric-type nonvolatile semiconductor memory comprising a plurality of bit lines and a plurality of memory cells, each memory cell comprising a first electrode, a ferroelectric layer formed at least on said first electrode and a second electrode formed on said ferroelectric layer, a plurality of the memory cells belonging to one of two or more thermal history groups having different thermal histories with regard to their production processes, data of 1 bit being to be stored in one of memory cells forming a pair, another data of 1 bit being to be stored in the other of said memory cells, a pair of said memory cells being connected to a pair of the bit lines, a pair of the bit lines being connected to a differential sense amplifier, wherein, when data stored in one of said memory cells forming a pair is read out, a reference potential is provided to the bit line connected to the other of said memory cells, when another data stored in the other of said memory cells is read out, a reference potential is provided to the bit line connected to the one of said memory cells, and a reference potential of the same level is provided to the bit lines connected to the memory cells belonging to the same thermal history group, and reference potentials of different levels are provided to the bit lines connected to the memory cells belonging to the different thermal history groups.