公开(公告)号：US20240104012A1

公开(公告)日：2024-03-28

申请号：US18528541

申请日：2023-12-04

申请人： Google LLC

发明人： Lukasz Lew

IPC分类号： G06F12/02 ,  G06F7/523 ,  G06N3/063 ,  G06N20/00

CPC分类号： G06F12/0207 ,  G06F7/523 ,  G06N3/063 ,  G06N20/00 ,  G06F2212/2024

摘要： Methods, systems, and apparatus, including computer programs encoded on computer storage media, for performing topological scheduling on a machine-learning accelerator having an array of tiles. One of the methods includes performing, at each time step of a plurality of time steps corresponding respectively to columns within each of a plurality of wide columns of the tile array, operations comprising: performing respective multiplications using tiles in a respective tile column for the time step, computing a respective output result for each respective tile column for the time step including computing a sum of results of the multiplications for the tile column, and storing the respective output result for the tile column in a particular output RAM having a location within the same tile column and on a row from which the output result will be read by a subsequent layer of the model.

公开(公告)号：US20190250916A1

公开(公告)日：2019-08-15

申请号：US16336884

申请日：2016-09-30

申请人： Intel Corporation

发明人： Patrick LU ,  Karthik KUMAR ,  Thomas WILLHALM ,  Francesc GUIM BERNAT ,  Martin P. DIMITROV

IPC分类号： G06F9/30 ,  G06F12/0862 ,  G06F12/0811

CPC分类号： G06F9/30047 ,  G06F9/30043 ,  G06F9/383 ,  G06F12/0811 ,  G06F12/0862 ,  G06F2212/1024 ,  G06F2212/2022 ,  G06F2212/2024 ,  G06F2212/205 ,  G06F2212/6028

摘要： An apparatus is described. The apparatus includes main memory control logic circuitry comprising prefetch intelligence logic circuitry. The prefetch intelligence circuitry to determine, from a read result of a load instruction, an address for a dependent load that is dependent on the read result and direct a read request for the dependent load to a main memory to fetch the dependent load's data.

公开(公告)号：US20180267899A1

公开(公告)日：2018-09-20

申请号：US15986167

申请日：2018-05-22

申请人： Everspin Technologies, Inc.

发明人： Thomas Andre ,  Syed M. Alam ,  Chitra Subramanian ,  Javed S. Barkatullah

IPC分类号： G06F12/0893 ,  G06F3/06 ,  G11C7/10 ,  G06F12/0802 ,  G11C11/16 ,  G11C16/32 ,  G11C7/22 ,  G06F12/0862

CPC分类号： G06F12/0893 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0683 ,  G06F12/0215 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0851 ,  G06F12/0855 ,  G06F12/0862 ,  G06F2212/1024 ,  G06F2212/2024 ,  G06F2212/3042 ,  G06F2212/6026 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/22 ,  G11C11/1693 ,  G11C16/32 ,  G11C2207/2245 ,  G11C2207/2272 ,  Y02D10/13

摘要： A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.

公开(公告)号：US20180267891A1

公开(公告)日：2018-09-20

申请号：US15882847

申请日：2018-01-29

申请人： Rambus Inc.

发明人： Thomas A. Sheffler ,  Lawrence Lai ,  Liang Peng ,  Bohuslav Rychlik

IPC分类号： G06F12/02 ,  G11C7/10 ,  G11C8/10 ,  G11C7/22

CPC分类号： G06F12/023 ,  G06F2212/2024 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/22 ,  G11C8/10 ,  G11C2207/107 ,  H05K999/99

摘要： A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values.

公开(公告)号：US10007468B2

公开(公告)日：2018-06-26

申请号：US15716360

申请日：2017-09-26

申请人： HUAWEI TECHNOLOGIES CO., LTD.

发明人： Yan Li

IPC分类号： G06F12/00 ,  G06F3/06 ,  G06F12/02 ,  G06F21/79 ,  G11C16/04 ,  G06F12/0893 ,  G06F12/0888

CPC分类号： G06F3/0652 ,  G06F3/0619 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0888 ,  G06F12/0893 ,  G06F21/79 ,  G06F2212/1032 ,  G06F2212/1052 ,  G06F2212/2022 ,  G06F2212/2024 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2221/2143 ,  G11C16/0483

摘要： A data erasing method and apparatus applied to a flash memory. The method includes receiving a data erasing instruction, where the data erasing instruction instructs to erase data or at least one data section of data sections corresponding to data, when the data erasing instruction instructs to erase the data, searching for recorded storage addresses of all the data sections corresponding to the data, and erasing all the data sections corresponding to the data according to the storage addresses that are found; and when the data erasing instruction instructs to erase the at least one data section of the data sections corresponding to the data, searching for a recorded storage address of the at least one data section, and erasing the at least one data section according to the storage address that is found.

公开(公告)号：US09899086B2

公开(公告)日：2018-02-20

申请号：US14163666

申请日：2014-01-24

申请人： IMEC

发明人： Francky Catthoor ,  Komalan Manu Perumkunnil ,  Stefan Cosemans

IPC分类号： G06F12/00 ,  G11C14/00 ,  G06F12/0893 ,  G06F12/0897 ,  G06F12/02 ,  G11C13/00

CPC分类号： G11C14/009 ,  G06F12/0246 ,  G06F12/0893 ,  G06F12/0897 ,  G06F2212/1028 ,  G06F2212/2024 ,  G06F2212/222 ,  G06F2212/454 ,  G06F2212/7201 ,  G11C13/0002 ,  Y02D10/13

摘要： A microcomputer comprising a microprocessor unit and a first memory unit is disclosed. In one aspect, the microprocessor unit comprises at least one functional unit and at least one register. Further, the at least one register is a wide register comprising a plurality of second memory units which are capable to each contain one word, the wide register being adapted so that the second memory units are simultaneously accessible by the first memory unit, and at least part of the second memory units are separately accessible by the at least one functional unit. Further, the first memory unit is an embedded non-volatile memory unit.

公开(公告)号：US20180018126A1

公开(公告)日：2018-01-18

申请号：US15716360

申请日：2017-09-26

申请人： HUAWEI TECHNOLOGIES CO., LTD.

发明人： Yan LI

IPC分类号： G06F3/06 ,  G06F21/79 ,  G06F12/02 ,  G11C16/04

CPC分类号： G06F3/0652 ,  G06F3/0619 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0888 ,  G06F12/0893 ,  G06F21/79 ,  G06F2212/1032 ,  G06F2212/1052 ,  G06F2212/2022 ,  G06F2212/2024 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2221/2143 ,  G11C16/0483

摘要： A data erasing method and apparatus applied to a flash memory. The method includes receiving a data erasing instruction, where the data erasing instruction instructs to erase data or at least one data section of data sections corresponding to data, when the data erasing instruction instructs to erase the data, searching for recorded storage addresses of all the data sections corresponding to the data, and erasing all the data sections corresponding to the data according to the storage addresses that are found; and when the data erasing instruction instructs to erase the at least one data section of the data sections corresponding to the data, searching for a recorded storage address of the at least one data section, and erasing the at least one data section according to the storage address that is found.

公开(公告)号：US09823878B2

公开(公告)日：2017-11-21

申请号：US14852968

申请日：2015-09-14

申请人： Huawei Technologies Co., Ltd.

发明人： Yan Li

IPC分类号： G06F12/00 ,  G06F3/06 ,  G06F12/02 ,  G06F21/79 ,  G06F12/0893 ,  G06F12/0888 ,  G11C16/04

CPC分类号： G06F3/0652 ,  G06F3/0619 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0888 ,  G06F12/0893 ,  G06F21/79 ,  G06F2212/1032 ,  G06F2212/1052 ,  G06F2212/2022 ,  G06F2212/2024 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2221/2143 ,  G11C16/0483

摘要： A data erasing method and apparatus applied to a flash memory. The method includes receiving a data erasing instruction, where the data erasing instruction instructs to erase data or at least one data section of data sections corresponding to data, when the data erasing instruction instructs to erase the data, searching for recorded storage addresses of all the data sections corresponding to the data, and erasing all the data sections corresponding to the data according to the storage addresses that are found; and when the data erasing instruction instructs to erase the at least one data section of the data sections corresponding to the data, searching for a recorded storage address of the at least one data section, and erasing the at least one data section according to the storage address that is found. The data erasing method and apparatus may be used in an implementation technology of the flash memory.

公开(公告)号：US20170329522A1

公开(公告)日：2017-11-16

申请号：US15527781

申请日：2014-12-31

申请人： Shannon Systems Ltd.

发明人： Xueshi YANG

IPC分类号： G06F3/06 ,  G06F12/02 ,  G06F12/06

CPC分类号： G06F3/064 ,  G06F3/0616 ,  G06F3/0688 ,  G06F11/1076 ,  G06F12/0253 ,  G06F12/06 ,  G06F2212/1036 ,  G06F2212/2022 ,  G06F2212/2024 ,  G06F2212/262 ,  G06F2212/7201 ,  G06F2212/7205

摘要： “A RAID system and method based on a solid-state storage medium. The system includes a plurality of solid-state storage devices and a main control unit. Each solid-state storage device includes a solid-state storage medium and a controller for controlling reading and writing of the solid-state storage medium. The main control unit is electrically connected to the controller of each of the solid-state storage devices in a RAID array. The main control unit is used for performing address mapping from a logical block address in the RAID array to a physical block address of the flash memory solid-state storage device. The address mapping and the RAID function can be integrated to solve the problems of write amplification and low performance. The unified management of address mapping of the solid-state storage devices can be implemented to improve the efficiency of garbage collection and wear leveling of the solid-state storage system.”

公开(公告)号：US20170220487A1

公开(公告)日：2017-08-03

申请号：US15416426

申请日：2017-01-26

申请人： YONG-WON JUNG ,  Sungkyoung KIM ,  Jun-Ho SEO ,  Taekkyun SHIN ,  Sang-hwa JIN

发明人： YONG-WON JUNG ,  Sungkyoung KIM ,  Jun-Ho SEO ,  Taekkyun SHIN ,  Sang-hwa JIN

IPC分类号： G06F12/14 ,  G06F3/06

CPC分类号： G06F12/1408 ,  G06F12/0238 ,  G06F12/0875 ,  G06F21/78 ,  G06F2212/1028 ,  G06F2212/1052 ,  G06F2212/2024 ,  G06F2212/2515 ,  G06F2212/402 ,  G06F2212/7203 ,  G06F2221/2113 ,  Y02D10/13

摘要： A system-on-chip includes a magnetic random access memory and a security interface. The magnetic random access memory includes a plurality of memory areas, each of the plurality of memory areas having a different security level. The security interface circuitry configured to: identify a memory area from among the plurality of memory areas based on a received memory address associated with a received memory command; determine a security level associated with the identified memory area; and perform a memory operation on received data based on the received memory command and the determined security level.