公开(公告)号：US20120083913A1

公开(公告)日：2012-04-05

申请号：US12897021

申请日：2010-10-04

申请人： Robert D. Herzl ,  Robert S. Horton ,  Kenneth A. Lauricella ,  David W. Milton ,  Clarence R. Ogilvie ,  Nitin Sharma ,  Tad J. Wilder ,  Charles B. Winn

发明人： Robert D. Herzl ,  Robert S. Horton ,  Kenneth A. Lauricella ,  David W. Milton ,  Clarence R. Ogilvie ,  Nitin Sharma ,  Tad J. Wilder ,  Charles B. Winn

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/72

摘要： A method of forming and electrical structure. The method includes determining that a first semiconductor device requires an engineering change order (ECO). An additional structure layer required to implement the ECO is determined. A first insertion point location for inserting the additional structure layer within the first semiconductor device is selected. The first insertion point location is associated with a second insertion point location within a design for a second semiconductor device. The second semiconductor device is generated in accordance with the first ECO. The second semiconductor device comprises second structures. The second structures comprise same structures as first structures in the first semiconductor device. The second structures are formed in locations within the second semiconductor device that are associated with locations in the first semiconductor device comprising the first structures. The second semiconductor device comprises the additional structure layer located within the second insertion point location.

摘要翻译： 一种形成和电气结构的方法。 该方法包括确定第一半导体器件需要工程改变顺序（ECO）。 确定实现ECO所需的附加结构层。 选择用于将附加结构层插入第一半导体器件内的第一插入点位置。 第一插入点位置与用于第二半导体器件的设计内的第二插入点位置相关联。 根据第一ECO产生第二半导体器件。 第二半导体器件包括第二结构。 第二结构包括与第一半导体器件中的第一结构相同的结构。 第二结构形成在第二半导体器件内的与包含第一结构的第一半导体器件中的位置相关联的位置。 第二半导体器件包括位于第二插入点位置内的附加结构层。

公开(公告)号：US20090045839A1

公开(公告)日：2009-02-19

申请号：US11876263

申请日：2007-10-22

申请人： Robert D. HERZL ,  Robert S. Horton ,  Kenneth A. Lauricella ,  David W. Milton ,  Clarence R. Ogilvie ,  Paul M. Schanely ,  Nitin Sharma ,  Tad J. Wilder ,  Charles B. Winn

发明人： Robert D. HERZL ,  Robert S. Horton ,  Kenneth A. Lauricella ,  David W. Milton ,  Clarence R. Ogilvie ,  Paul M. Schanely ,  Nitin Sharma ,  Tad J. Wilder ,  Charles B. Winn

IPC分类号： H03K19/177 ,  G06F17/50

CPC分类号： G06F17/505

摘要： A chip design methodology and an integrated circuit chip. The methodology includes providing a plurality of logic gates in a net list, wherein each of the logic gates comprises at least one spare input, synthesizing the net list, and connecting the spare inputs for performing an engineering change late in the design process. The invention is also directed to a design structure on which a circuit resides.

摘要翻译： 芯片设计方法和集成电路芯片。 该方法包括在网络列表中提供多个逻辑门，其中每个逻辑门包括至少一个备用输入，合成网络列表，以及在设计过程的后期连接用于执行工程变更的备用输入。 本发明还涉及电路所在的设计结构。

公开(公告)号：US06385685B1

公开(公告)日：2002-05-07

申请号：US09833871

申请日：2001-04-12

申请人： Timothy J. Dell ,  Bruce G. Hazelzet ,  Mark W. Kellogg ,  Clarence R. Ogilvie ,  Paul C. Stabler

发明人： Timothy J. Dell ,  Bruce G. Hazelzet ,  Mark W. Kellogg ,  Clarence R. Ogilvie ,  Paul C. Stabler

IPC分类号： G06F1338

CPC分类号： G11C5/066

摘要： A serial bus and connection to a device on a computer system through a system memory controller is provided on a memory card having a DSP and a memory bus controller to allow the DSP on the memory card to gain access to the system device without using the system memory bus. The serial bus is a two wire serial bus connecting the device to the DSP through the system memory controller. If more than one memory card is present with DSPs or more than one device is contending for access, the system memory controller or arbitrate the access of each memory card or contending device. In such case the serial bus will signal the system memory controller when it wants access to the particular device, and the system memory controller will act as arbitrator to grant or not grant access to the particular memory card or device requesting access. If access is granted the bus memory controller outputs the required control or command word on the serial bus followed by the address and the required data. This serial information is received by the system memory controller which packets it, and, upon completion, outputs the information rapidly on a parallel bus, e.g. a PCI bus to the device which needs the information.

公开(公告)号：US4768161A

公开(公告)日：1988-08-30

申请号：US930176

申请日：1986-11-14

申请人： Roland A. Bechade ,  William K. Hoffman ,  Clarence R. Ogilvie

发明人： Roland A. Bechade ,  William K. Hoffman ,  Clarence R. Ogilvie

IPC分类号： G06F7/53 ,  G06F7/508 ,  G06F7/52

CPC分类号： G06F7/5312 ,  G06F2207/3876

摘要： Digital binary multipliers are provided which include first and second inverting full adders, each having first, second and third input terminals and first and second output terminals, the first output terminal of the first adder being connected to the first input terminal of the second adder with the first, second and third input terminals and the first and second output terminals of the second adder having a relationship with respect to the input and output terminals of the first adder such that corresponding input and output terminals have opposite signal polarities or complementary terminals, i.e., when one of these input or output terminals of the first adder has a true polarity signal, its corresponding input or output terminal of the second adder has a complemented polarity signal.

摘要翻译： 提供了数字二进制乘法器，其包括第一和第二反相全加器，每个具有第一，第二和第三输入端以及第一和第二输出端，第一加法器的第一输出端连接到第二加法器的第一输入端， 第二加法器的第一，第二和第三输入端和第一和第二输出端相对于第一加法器的输入和输出端具有关系，使得相应的输入和输出端具有相反的信号极性或互补端，即 当第一加法器的这些输入或输出端之一具有真正的极性信号时，其对应的第二加法器的输入或输出端具有互补的极性信号。

公开(公告)号：US10169500B2

公开(公告)日：2019-01-01

申请号：US13204812

申请日：2011-08-08

申请人： Margaret R. Charlebois ,  Rashmi D. Chatty ,  Christopher D. Hanudel ,  Robert D. Herzl ,  David W. Milton ,  Clarence R. Ogilvie ,  Matthew P. Szafir ,  Tad J. Wilder

发明人： Margaret R. Charlebois ,  Rashmi D. Chatty ,  Christopher D. Hanudel ,  Robert D. Herzl ,  David W. Milton ,  Clarence R. Ogilvie ,  Matthew P. Szafir ,  Tad J. Wilder

IPC分类号： G06F19/00 ,  G06F17/50

摘要： Embodiments of the invention provide a method, system, and program product for predicting a delay of a critical path. In one embodiment, the invention provides a method of predicting a delay of at least one critical path of an integrated circuit, the method comprising: determining a delay of at least one ring oscillator on the integrated circuit; and calculating a predicted delay for the at least one critical path delay based on a delay of components of the critical path at a corner condition, a wire delay of the at least one critical path, a delay of the at least one ring oscillator at a corner condition, and the determined delay of the at least one ring oscillator.

公开(公告)号：US20140028365A1

公开(公告)日：2014-01-30

申请号：US13558498

申请日：2012-07-26

申请人： Margaret R. Charlebois ,  Rashmi D. Chatty ,  Christopher D. Hanudel ,  Robert D. Herzl ,  David W. Milton ,  Clarence R. Ogilvie ,  Paul M. Schanely ,  Matthew P. Szafir ,  Tad J. Wilder

发明人： Margaret R. Charlebois ,  Rashmi D. Chatty ,  Christopher D. Hanudel ,  Robert D. Herzl ,  David W. Milton ,  Clarence R. Ogilvie ,  Paul M. Schanely ,  Matthew P. Szafir ,  Tad J. Wilder

IPC分类号： H03H11/26

CPC分类号： H03K3/0315

摘要： Aspects of the invention provide a circuit structure that automatically monitors a plurality of ring oscillators and dynamically selects the fastest or the slowest ring oscillator for feedback into the plurality of ring oscillators. In one embodiment, a circuit includes: a plurality of delay elements, each delay element associated with a ring oscillator; a first logic gate for receiving outputs of each of the delay elements; a second logic gate for receiving outputs of each of the delay elements; and a multiplexer for receiving an output of the first logic gate and an output of the second logic gate and choosing one of the outputs, wherein a selection for the multiplexer is based on an output of the multiplexer. To select the fastest ring oscillator, a second multiplexer is provided.

摘要翻译： 本发明的方面提供了一种电路结构，其自动监测多个环形振荡器并且动态地选择最快或最慢的环形振荡器用于反馈到多个环形振荡器中。 在一个实施例中，电路包括：多个延迟元件，每个延迟元件与环形振荡器相关联; 用于接收每个延迟元件的输出的第一逻辑门; 第二逻辑门，用于接收每个延迟元件的输出; 以及多路复用器，用于接收第一逻辑门的输出和第二逻辑门的​​输出并选择输出之一，其中多路复用器的选择基于多路复用器的输出。 为了选择最快的环形振荡器，提供了第二个多路复用器。

公开(公告)号：US08341588B2

公开(公告)日：2012-12-25

申请号：US12897021

申请日：2010-10-04

申请人： Robert D. Herzl ,  Robert S. Horton ,  Kenneth A. Lauricella ,  David W. Milton ,  Clarence R. Ogilvie ,  Paul M. Schanely ,  Nitin Sharma ,  Tad J. Wilder ,  Charles B. Winn

发明人： Robert D. Herzl ,  Robert S. Horton ,  Kenneth A. Lauricella ,  David W. Milton ,  Clarence R. Ogilvie ,  Paul M. Schanely ,  Nitin Sharma ,  Tad J. Wilder ,  Charles B. Winn

IPC分类号： G06F15/04 ,  G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/72

摘要： A method of forming and electrical structure. The method includes determining that a first semiconductor device requires an engineering change order (ECO). An additional structure layer required to implement the ECO is determined. A first insertion point location for inserting the additional structure layer within the first semiconductor device is selected. The first insertion point location is associated with a second insertion point location within a design for a second semiconductor device. The second semiconductor device is generated in accordance with the first ECO. The second semiconductor device comprises second structures. The second structures comprise same structures as first structures in the first semiconductor device. The second structures are formed in locations within the second semiconductor device that are associated with locations in the first semiconductor device comprising the first structures. The second semiconductor device comprises the additional structure layer located within the second insertion point location.

摘要翻译： 一种形成和电气结构的方法。 该方法包括确定第一半导体器件需要工程改变顺序（ECO）。 确定实现ECO所需的附加结构层。 选择用于将附加结构层插入第一半导体器件内的第一插入点位置。 第一插入点位置与用于第二半导体器件的设计中的第二插入点位置相关联。 根据第一ECO产生第二半导体器件。 第二半导体器件包括第二结构。 第二结构包括与第一半导体器件中的第一结构相同的结构。 第二结构形成在第二半导体器件内的与包含第一结构的第一半导体器件中的位置相关联的位置。 第二半导体器件包括位于第二插入点位置内的附加结构层。

公开(公告)号：US08060845B2

公开(公告)日：2011-11-15

申请号：US12173222

申请日：2008-07-15

申请人： Robert D. Herzl ,  Robert S. Horton ,  Kenneth A. Lauricella ,  David W. Milton ,  Clarence R. Ogilvie ,  Paul M. Schanely ,  Nitin Sharma ,  Tad J. Wilder ,  Charles B. Winn

发明人： Robert D. Herzl ,  Robert S. Horton ,  Kenneth A. Lauricella ,  David W. Milton ,  Clarence R. Ogilvie ,  Paul M. Schanely ,  Nitin Sharma ,  Tad J. Wilder ,  Charles B. Winn

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A method is provided for updating an existing netlist to reflect a design change. A register transfer level (RTL) design incorporating the design change and the existing netlist are provided to a synthesis tool. The existing netlist is set to a read-only condition to prevent a change to the existing netlist. The design and the read-only existing netlist are processed with the synthesis tool reusing logic structures from the read-only existing netlist by performing an optimization of the design and the read-only existing netlist with an objective to minimize the design space. The optimization is constrained by the read-only existing netlist. A result is generated by the synthesis tool including the existing netlist and a new portion of a netlist reflecting the design change.

摘要翻译： 提供了一种用于更新现有网表以反映设计变更的方法。 将设计更改和现有网表的注册传输级别（RTL）设计提供给综合工具。 现有的网表设置为只读条件，以防止更改现有的网表。 通过执行设计优化和只读现有网表的综合工具对来自只读现有网表的逻辑结构进行重用，设计和只读现有网表被处理，目的是最小化设计空间。 优化受只读现有网表约束。 综合工具产生的结果包括现有网表和反映设计变更的网表的新部分。

公开(公告)号：US07206886B2

公开(公告)日：2007-04-17

申请号：US11064569

申请日：2005-02-24

申请人： Robert S. Horton ,  Clarence R. Ogilvie ,  Charles S. Woodruff

发明人： Robert S. Horton ,  Clarence R. Ogilvie ,  Charles S. Woodruff

IPC分类号： G06F13/00

CPC分类号： G06F13/4013

摘要： A bus bridge for coupling between a first bus and a second includes: at least one data buffer; data load logic and data unload logic. The data load logic places received data in the at least one data buffer, wherein the data is received at the bus bridge from across the first bus in a first data ordering. The data unload logic automatically translates the received data from the first data ordering to a second data ordering during unloading of the data from the at least one data buffer for transfer across the second bus, wherein the first data ordering and the second data ordering are each a different one of a linear data ordering and an interleaved data ordering.

摘要翻译： 用于在第一总线和第二总线之间耦合的总线桥包括：至少一个数据缓冲器; 数据加载逻辑和数据卸载逻辑。 数据加载逻辑将接收到的数据放置在至少一个数据缓冲器中，其中数据在总线桥接处以第一数据顺序跨越第一总线接收。 在卸载来自至少一个数据缓冲器的数据的第一数据排序期间，数据卸载逻辑自动将所接收的数据从第一数据排序转换为第二数据排序，其中第一数据排序和第二数据排序分别为 线性数据排序和交织数据排序中的不同之一。

公开(公告)号：US6138200A

公开(公告)日：2000-10-24

申请号：US94084

申请日：1998-06-09

申请人： Clarence R. Ogilvie

发明人： Clarence R. Ogilvie

IPC分类号： G06F13/372 ,  G06F13/14

CPC分类号： G06F13/372

摘要： A system and method for arbitrating amongst a plurality of applications requesting bus access. Based on the applications requesting bus access, a bus frame is calculated, and a plurality of bus duration time slots within the bus frame are determined. For each bus duration time slot, a priority is assigned to each application requesting bus control and a bus allocation table is created. A bus master controller then allocates control during each bus duration time slot in accordance with the priorities in the bus allocation table.

摘要翻译： 一种用于在请求总线访问的多个应用中进行仲裁的系统和方法。 基于请求总线访问的应用，计算总线帧，并且确定总线帧内的多个总线持续时间时隙。 对于每个总线持续时间段，优先级被分配给请求总线控制的每个应用，并且创建总线分配表。 然后，总线主控制器根据总线分配表中的优先级在每个总线持续时间段内分配控制。