公开(公告)号：US06534921B1

公开(公告)日：2003-03-18

申请号：US09708737

申请日：2000-11-09

申请人： Sang-Hun Seo ,  Kyeong-Koo Chi ,  Ji-Soo Kim ,  Chang-Woong Chu ,  Seung-Pil Chung

发明人： Sang-Hun Seo ,  Kyeong-Koo Chi ,  Ji-Soo Kim ,  Chang-Woong Chu ,  Seung-Pil Chung

IPC分类号： H01J724

CPC分类号： H01L21/31138 ,  B08B7/0035 ,  G03F7/427 ,  H05H1/44

摘要： A method of removing metal-containing polymeric material and ion implanted or plasma damaged photoresist from a surface using a plasma jet system, by generating radicals having high energy and high density from atmospheric plasma by introducing a reactant gas to the plasma, and placing the surface at a distance from the plasma, whereby ionic reaction on the surface is minimized while the removing action of the radicals on the surface is maintained.

摘要翻译： 通过使用等离子体喷射系统从表面去除含金属的聚合物材料和离子注入或等离子体损伤的光致抗蚀剂的方法，通过向等离子体引入反应气体，通过从等离子体引入具有高能量和高密度的自由基，并将表面 距离等离子体一定距离，由此表面上的离子反应被最小化，同时维持表面上的自由基的去除作用。

公开(公告)号：US20110053379A1

公开(公告)日：2011-03-03

申请号：US12679008

申请日：2008-09-16

申请人： Kyeong-Koo Chi ,  Jonathan Kim

发明人： Kyeong-Koo Chi ,  Jonathan Kim

IPC分类号： H01L21/3065 ,  C23F1/08

CPC分类号： H01L21/31116

摘要： A method for etching a dielectric layer is provided. The dielectric layer is disposed over a substrate and below a patterned mask having a line-space pattern. The method includes (a) providing an etchant gas comprising CF4, COS, and an oxygen containing gas, (b) forming a plasma from the etchant gas, and (c) etching the dielectric layer into the line-space pattern through the mask with the plasma from the etchant gas. The gas flow rate of CF4 may have a ratio greater than 50% of a total gas flow rate of all reactive gas components. The gas flow rate of COS may be between 1% and 50%. The method reduces bowing in etching of the dielectric layer by adding COS to the etchant gas.

摘要翻译： 提供了蚀刻介电层的方法。 电介质层设置在衬底上并且在具有线间距图案的图案化掩模之下。 该方法包括（a）提供包括CF 4，COS和含氧气体的蚀刻剂气体，（b）从蚀刻剂气体形成等离子体，和（c）通过掩模将电介质层蚀刻成线 - 空间图案， 来自蚀刻剂气体的等离子体。 CF4的气体流量可以具有大于所有反应气体组分的总气体流量的50％的比率。 COS的气体流量可以在1％和50％之间。 该方法通过向蚀刻剂气体中添加COS来减少蚀刻介电层的弯曲度。

公开(公告)号：US07547636B2

公开(公告)日：2009-06-16

申请号：US11671342

申请日：2007-02-05

申请人： Kyeong-Koo Chi ,  Erik A. Edelberg

发明人： Kyeong-Koo Chi ,  Erik A. Edelberg

IPC分类号： H01L21/302

CPC分类号： H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76816

摘要： A method for selectively etching an ultra high aspect ratio feature dielectric layer through a carbon based mask in an etch chamber is provided. A flow of an etch gas is provided, comprising a fluorocarbon containing molecule and an oxygen containing molecule to the etch chamber. A pulsed bias RF signal is provided. An energizing RF signal is provided to transform the etch gas to a plasma.

摘要翻译： 提供了一种通过蚀刻室中的基于碳的掩模来选择性地蚀刻超高宽比特征介电层的方法。 提供蚀刻气体的流动，其包括含氟碳分子和含氧分子到蚀刻室。 提供脉冲偏置RF信号。 提供激励RF信号以将蚀刻气体转换成等离子体。

公开(公告)号：US20060027856A1

公开(公告)日：2006-02-09

申请号：US11190314

申请日：2005-07-26

申请人： Seung-Pil Chung ,  Jong-Ho Park ,  Kyeong-Koo Chi ,  Dong-Hyun Kim

发明人： Seung-Pil Chung ,  Jong-Ho Park ,  Kyeong-Koo Chi ,  Dong-Hyun Kim

IPC分类号： H01L21/8238 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A nonvolatile memory device includes a semiconductor substrate, a device isolation film, a tunnel insulation film, a plurality of floating gates, an inter-gate dielectric film, and a control gate pattern. Trenches are formed in the substrate that define active regions therebetween. The device isolation film is in the trenches in the substrate. The tunnel insulation film is on the active regions of the substrate. The plurality of floating gates are each on the tunnel insulation film over the active regions of the substrate. The inter-gate dielectric film extends across the floating gates and the device isolation film. The control gate pattern is on the inter-gate dielectric film and extends across the floating gates. A central region of the device isolation film in the trenches has an upper major surface that is recessed below an upper major surface of a surrounding region of the device isolation film in the trenches. An edge of the recessed central region of the device isolation film is aligned with a sidewall of an adjacent one of the floating gates.

摘要翻译： 非易失性存储器件包括半导体衬底，器件隔离膜，隧道绝缘膜，多个浮置栅极，栅极间电介质膜和控制栅极图案。 沟槽形成在衬底中，其间限定有效区域。 器件隔离膜位于衬底中的沟槽中。 隧道绝缘膜位于衬底的有源区上。 多个浮置栅极分别位于衬底的有源区上的隧道绝缘膜上。 栅极间电介质膜延伸穿过浮栅和器件隔离膜。 控制栅极图案在栅极间电介质膜上并且跨越浮动栅极延伸。 沟槽中的器件隔离膜的中心区域具有在沟槽中的器件隔离膜的周围区域的上主表面下方凹陷的上主表面。 器件隔离膜的凹入的中心区域的边缘与相邻的一个浮动栅极的侧壁对准。