公开(公告)号：US11502948B2

公开(公告)日：2022-11-15

申请号：US17108002

申请日：2020-12-01

Applicant: Mellanox Technologies, Ltd

Inventor： Boris Pismenny ,  Miriam Menes ,  Idan Burstein ,  Liran Liss ,  Noam Bloch ,  Ariel Shahar

IPC: H04L45/00 ,  H04L45/42 ,  G06F11/10 ,  H04L69/163 ,  H04L69/22

Abstract: A system includes a host processor, which has a host memory and is coupled to store data in a non-volatile memory in accordance with a storage protocol. A network interface controller (NIC) receives data packets conveyed over a packet communication network from peer computers containing, in payloads of the data packets, data records that encode data in accordance with the storage protocol for storage in the non-volatile memory. The NIC processes the data records in the data packets that are received in order in each flow from a peer computer and extracts and writes the data to the host memory, and when a data packet arrives out of order, writes the data packet to the host memory without extracting the data and processes the data packets in the flow so as to recover context information for use in processing the data records in subsequent data packets in the flow.

公开(公告)号：US20220337386A1

公开(公告)日：2022-10-20

申请号：US17231747

申请日：2021-04-15

Applicant: Mellanox Technologies, Ltd.

Inventor： Juan Jose Vegas Olmos ,  Elad Mentovich ,  Liran Liss

IPC: H04L7/00 ,  H04L25/03 ,  H04B10/69 ,  H04B10/40

Abstract: Embodiments are disclosed for facilitating an end-to-end link channel with one or more lookup tables for equalization. An example system includes a first transceiver and a second transceiver. The first transceiver includes a clock data recovery (CDR) circuit configured to receive communication data from a switch and to manage a lookup table associated with equalization of the communication data. The first transceiver also includes a first driver circuit communicatively coupled to the CDR circuit and configured to generate an electrical signal associated with the communication data. The second transceiver includes a second driver circuit, communicatively coupled to the first transceiver, that is configured to receive the electrical signal from the first transceiver and to modulate a laser source based on the electrical signal to generate an optical signal via the laser source.

公开(公告)号：US20200259803A1

公开(公告)日：2020-08-13

申请号：US16858874

申请日：2020-04-27

Applicant: Mellanox Technologies, Ltd.

Inventor： Adi Menachem ,  Liran Liss ,  Boris Pismenny

IPC: H04L29/06 ,  H04L9/08 ,  G06F21/53 ,  G06F21/60 ,  H04L9/32 ,  H04L9/14 ,  G06F9/455

Abstract: Computing apparatus includes a host processor, which runs a virtual machine monitor (VMM), which supports a plurality of virtual machines and includes a cryptographic security software module. A network interface controller (NIC) links the host processor to a network so as to transmit and receive data packets from and to the virtual machines and includes a cryptographic security hardware logic module, which when invoked by the VMM, applies the cryptographic security protocol to the data packets while maintaining a state context of the protocol with respect to each of the virtual machines. Upon encountering an exception in applying the cryptographic security protocol, the NIC transfers the data packet, together with the state context of the cryptographic security protocol with respect to the given virtual machine, to the cryptographic security software module for processing.

公开(公告)号：US20190140979A1

公开(公告)日：2019-05-09

申请号：US16012826

申请日：2018-06-20

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan Levi ,  Liran Liss ,  Haggai Eran ,  Noam Bloch ,  Idan Burstein ,  Lior Narkis ,  Avraham Ganor

IPC: H04L12/933 ,  G06F9/455 ,  G06F13/40

Abstract: A network interface controller that is connected to a host and a packet communications network. The network interface controller includes electrical circuitry configured as a packet processing pipeline with a plurality of stages. It is determined in the network interface controller that at least a portion of the stages of the pipeline are acceleration-defined stages. Packets are processed in the pipeline by transmitting data to an accelerator from the acceleration-defined stages, performing respective acceleration tasks on the transmitted data in the accelerator, and returning processed data from the accelerator to receiving stages of the pipeline.

公开(公告)号：US20190116127A1

公开(公告)日：2019-04-18

申请号：US16159767

申请日：2018-10-15

Applicant: Mellanox Technologies, Ltd.

Inventor： Boris Pismenny ,  Liran Liss ,  Ilya Lesokhin ,  Haggai Eran ,  Adi Menachem

IPC: H04L12/833 ,  H04L29/06 ,  H04L12/931 ,  H04L12/851 ,  H04L29/08

Abstract: Packet processing apparatus includes a first interface coupled to a host processor and a second interface configured to transmit and receive data packets to and from a packet communication network. A memory holds context information with respect to one or more flows of the data packets conveyed between the host processor and the network in accordance with a reliable transport protocol and with respect to encoding, in accordance with a session-layer protocol, of data records that are conveyed in the payloads of the data packets in the one or more flows. Processing circuitry, coupled between the first and second interfaces, transmits and receives the data packets and includes acceleration logic, which encodes and decodes the data records in accordance with the session-layer protocol using the context information while updating the context information in accordance with the serial numbers and the data records of the transmitted data packets.

公开(公告)号：US10164905B2

公开(公告)日：2018-12-25

申请号：US14608265

申请日：2015-01-29

Applicant: Mellanox Technologies Ltd.

Inventor： Ofer Hayut ,  Noam Bloch ,  Shlomo Raikin ,  Liran Liss

IPC: H04L12/803 ,  H04L12/721 ,  H04L12/931

Abstract: A Network Interface Controller (NIC) includes a network interface, a peer interface and steering logic. The network interface is configured to receive incoming packets from a communication network. The peer interface is configured to communicate with a peer NIC not via the communication network. The steering logic is configured to classify the packets received over the network interface into first incoming packets that are destined to a local Central Processing Unit (CPU) served by the NIC, and second incoming packets that are destined to a remote CPU served by the peer NIC, to forward the first incoming packets to the local CPU, and to forward the second incoming packets to the peer NIC over the peer interface not via the communication network.

公开(公告)号：US09699110B2

公开(公告)日：2017-07-04

申请号：US14753159

申请日：2015-06-29

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Dror Goldenberg ,  Liran Liss ,  Shlomo Raikin

IPC: G06F15/173 ,  H04L12/927 ,  H04L12/911 ,  G06F9/52

CPC classification number: H04L47/801 ,  G06F9/52 ,  G06F2209/521 ,  G06F2209/522 ,  H04L47/743

Abstract: Lock access is managed in a data network having an initiator node and a remote target by issuing a lock command from a first process to the remote target via an initiator network interface controller to establish a lock on a memory location, and prior to receiving a reply to the lock command communicating a data access request to the memory location from the initiator network interface controller. Prior to receiving a reply to the data access request, an unlock command issues from the initiator network interface controller. The target network interface controller determines the lock content, and when permitted by the lock accesses the memory location. After accessing the memory location the target network interface controller executes the unlock command. When the lock prevents data access, the lock operation is retried a configurable number of times until data access is allowed or a threshold is exceeded.

公开(公告)号：US09639464B2

公开(公告)日：2017-05-02

申请号：US13628155

申请日：2012-09-27

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Haggai Eran ,  Shachar Raindel ,  Liran Liss ,  Noam Bloch

IPC: G06F12/08 ,  G06F12/1081

CPC classification number: G06F12/08 ,  G06F12/1081

Abstract: A method for data transfer includes receiving in an operating system of a host computer an instruction initiated by a user application running on the host processor identifying a page of virtual memory of the host computer that is to be used in receiving data in a message that is to be transmitted over a network to the host computer but has not yet been received by the host computer. In response to the instruction, the page is loaded into the memory, and upon receiving the message, the data are written to the loaded page.

公开(公告)号：US20160330112A1

公开(公告)日：2016-11-10

申请号：US15145983

申请日：2016-05-04

Applicant: Mellanox Technologies Ltd.

Inventor： Shachar Raindel ,  Shlomo Raikin ,  Liran Liss

IPC: H04L12/721 ,  H04L29/08 ,  H04L29/06 ,  H04L12/741

CPC classification number: H04L47/193 ,  G06F21/602 ,  H04L47/2441 ,  H04L63/04 ,  H04L63/0428 ,  H04L63/0485 ,  H04L67/327 ,  H04L69/22

Abstract: A data processing device includes a first packet communication interface for communication with at least one host processor via a network interface controller (NIC) and a second packet communication interface for communication with a packet data network. A memory holds a flow state table containing context information with respect to multiple packet flows conveyed between the host processor and the network via the first and second interfaces packet communication interfaces. Acceleration logic, coupled between the first and second packet communication interfaces, performs computational operations on payloads of packets in the multiple packet flows using the context information in the flow state table.

Abstract translation: 数据处理设备包括用于经由网络接口​​控制器（NIC）与至少一个主机处理器通信的第一分组通信接口和用于与分组数据网络通信的第二分组通信接口。 存储器保持流状态表，其包含关于经由第一和第二接口分组通信接口在主处理器和网络之间传送的多个分组流的上下文信息。 耦合在第一和第二分组通信接口之间的加速逻辑使用流状态表中的上下文信息对多个分组流中的分组的有效载荷执行计算操作。

公开(公告)号：US20160043965A1

公开(公告)日：2016-02-11

申请号：US14753159

申请日：2015-06-29

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Dror Goldenberg ,  Liran Liss ,  Shlomo Raikin

IPC: H04L12/927 ,  H04L29/08 ,  H04L12/911

CPC classification number: H04L47/801 ,  G06F9/52 ,  G06F2209/521 ,  G06F2209/522 ,  H04L47/743

Abstract: Lock access is managed in a data network having an initiator node and a remote target by issuing a lock command from a first process to the remote target via an initiator network interface controller to establish a lock on a memory location, and prior to receiving a reply to the lock command communicating a data access request to the memory location from the initiator network interface controller. Prior to receiving a reply to the data access request, an unlock command issues from the initiator network interface controller. The target network interface controller determines the lock content, and when permitted by the lock accesses the memory location. After accessing the memory location the target network interface controller executes the unlock command. When the lock prevents data access, the lock operation is retried a configurable number of times until data access is allowed or a threshold is exceeded.

Abstract translation: 在具有发起者节点和远程目标的数据网络中通过经由发起者网络接口控制器向远程目标发出锁定命令来向远程目标发出锁定访问，以在存储器位置上建立锁定，并且在接收到回复之前 该锁定命令从发起者网络接口控制器向存储器位置传送数据访问请求。 在接收到数据访问请求的答复之前，解锁命令从发起者网络接口控制器发出。 目标网络接口控制器确定锁定内容，并且当锁定允许访问存储器位置时。 访问内存位置后，目标网络接口控制器执行unlock命令。 当锁定阻止数据访问时，重试锁定操作可配置次数，直到允许数据访问或超过阈值。