公开(公告)号：US20220057960A1

公开(公告)日：2022-02-24

申请号：US17396529

申请日：2021-08-06

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Steffen Buch ,  Lance W. Dover

IPC: G06F3/06

Abstract: Methods, systems, and devices for host verification for a memory device are described. A memory device may receive a first value from a host device that is associated with an identification of the host device after an event. The memory device may transmit a second value to the host device that is based on the first value and comprises a random set of bits. The memory device may receive from the host device data or a command that comprises an encrypted third value that is based at least in part on the second value and a secret shared between the host device and the memory device. The memory device may also enable a functionality of the memory device based on the encrypted third value.

公开(公告)号：US20220057942A1

公开(公告)日：2022-02-24

申请号：US17453715

申请日：2021-11-05

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm

IPC: G06F3/06 ,  G11C29/26 ,  G06F11/16

Abstract: Apparatuses, systems, and methods related to determination of a match between data values stored by three or more arrays are described. A system using the data values may manage performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on whether the data values match. For instance, one apparatus described herein includes a plurality of arrays of memory cells formed on a single memory chip. The apparatus further includes comparator circuitry configured to compare data values stored by three arrays selected from the plurality to determine whether there is a match between the data values stored by the three arrays. The apparatus further includes an output component configured to output data values of one of two arrays of the three arrays responsive to determination of the match between the data values stored by the two arrays.

公开(公告)号：US11169730B2

公开(公告)日：2021-11-09

申请号：US16433891

申请日：2019-06-06

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Debra M. Bell

IPC: G11C29/00 ,  G06F3/06 ,  G06F11/10

Abstract: Methods, systems, and devices for scrub rate control for a memory device are described. For example, during a scrub operation, a memory device may perform an error correction operation on data read from a memory array of the memory device. The memory device may determine a quantity of errors detected or corrected during the scrub operation and determine a condition of the memory array based on the quantity of errors. The memory device may indicate the determined condition of the memory array to a host device. In some cases, the memory device may perform scrub operations based on one or more condition of the memory array. For example, as a condition of the memory array deteriorates, the memory device may perform scrub operations at an increased rate.

公开(公告)号：US11157437B2

公开(公告)日：2021-10-26

申请号：US16142095

申请日：2018-09-26

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm

IPC: G06F15/173 ,  H04L29/08 ,  H04W88/06 ,  H04W4/44

Abstract: Apparatuses, systems, and methods related to memory pooling between selected memory resources via a base station are described. A system using a memory pool formed as such may enable performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on increased access to data that may improve performance of a mission profile. For instance, one apparatus described herein includes a first memory resource, a first processor coupled to the first memory resource, and a wireless base station coupled to the first processor. The first memory resource, the first processor, and the base station are configured to enable formation of a memory pool between the first memory resource and a second memory resource at a vehicle responsive to a request to access the second memory resource from the first processor transmitted via the base station.

公开(公告)号：US11126498B2

公开(公告)日：2021-09-21

申请号：US16792820

申请日：2020-02-17

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: H03M13/00 ,  G06F11/10 ,  G11C29/44 ,  G11C7/10 ,  G11C29/42 ,  G06F11/07

Abstract: Methods, systems, and apparatus to selectively implement single-error correcting (SEC) operations or single-error correcting and double-error detecting (SECDED) operations, without noticeably impacting die size, for information received from a host device. For example, a host device may indicate that a memory system is to implement SECDED operations using one or more communications (e.g., messages). In another example, the memory system may be hardwired to perform SECDED for certain options. The memory system may adapt circuitry associated with SEC operations to implement SECDED operations without noticeably impacting die size. To implement SECDED operations using SEC circuitry, the memory system may include some additional circuitry to repurpose the SEC circuitry for SECDED operations.

公开(公告)号：US20210173562A1

公开(公告)日：2021-06-10

申请号：US17097766

申请日：2020-11-13

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G06F3/06

Abstract: Methods, systems, and devices for reset verification in a memory system are described. In some examples, a memory device may perform a reset operation and set a mode register to a first value based on performing the reset operation. The first value may be associated with a successful execution of the reset command. The memory device may transmit an indication to a host device based on determining the first value. The host device may determine from the received indication or from the first value stored in the mode register that the first value is associated with the successful execution of the reset command. Thus, the memory device, or the host device, or both may be configured to verify whether the reset operation is successful.

公开(公告)号：US20210098046A1

公开(公告)日：2021-04-01

申请号：US17076575

申请日：2020-10-21

Applicant: Micron Technology, Inc

Inventor： Kristen M. Hopper ,  Debra M. Bell ,  Aaron P. Boehm

IPC: G11C11/22 ,  G11C11/4074 ,  G06F11/34 ,  G06F11/30 ,  G11C11/4076

Abstract: Methods, systems, and devices for a current monitor for a memory device are described. A memory device may monitor potential degradation of memory cells on the device by monitoring the amount of current drawn by one or more memory cells. As the memory cells degrade, the current supplied to the memory cells may change (e.g., increase due to additional leakage current. The memory device may indirectly monitor changes in the current supplied to the memory cells by monitoring a voltage of a node of a transistor that controls the amount of current supplied to the array of memory cells. The voltage at the control node may be compared to a reference voltage to determine whether the two voltages differ by a threshold amount, indicating that the memory cells are drawing more current. The memory device may output a status indicator when the voltages differ, for example, by the threshold amount.

公开(公告)号：US20200374901A1

公开(公告)日：2020-11-26

申请号：US16989051

申请日：2020-08-10

Applicant: Micron Technology, Inc.

Inventor： Fa-Long Luo ,  Glen E. Hush ,  Aaron P. Boehm

IPC: H04W72/12 ,  H04B1/38 ,  G06F9/30

Abstract: Systems, apparatuses and method related to remotely executable instructions are described. A device may be wirelessly coupled to (e.g., physically separated) another device, which may be in a physically separate device. The another device may remotely execute instructions associated with performing various operations, which would have been entirely executed at the device absent the another device. The outputs obtained as a result of the execution may be transmitted, via the transceiver, back to the device via a wireless communication link (e.g., using resources of an ultra high frequency (UHF), super high frequency (SHF), extremely high frequency (EHF), and/or tremendously high frequency (THF) bands). The another device at which the instructions are remotely executable may include memory resources, processing resources, and transceiver resources; they may be configured to use one or several communication protocols over licensed or shared frequency spectrum bands, directly (e.g., device-to-device) or indirectly (e.g., via a base station).

公开(公告)号：US20200264950A1

公开(公告)日：2020-08-20

申请号：US16792820

申请日：2020-02-17

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G06F11/10 ,  G06F11/07 ,  G11C7/10 ,  G11C29/42 ,  G11C29/44

Abstract: Methods, systems, and apparatus to selectively implement single-error correcting (SEC) operations or single-error correcting and double-error detecting (SECDED) operations, without noticeably impacting die size, for information received from a host device. For example, a host device may indicate that a memory system is to implement SECDED operations using one or more communications (e.g., messages). In another example, the memory system may be hardwired to perform SECDED for certain options. The memory system may adapt circuitry associated with SEC operations to implement SECDED operations without noticeably impacting die size. To implement SECDED operations using SEC circuitry, the memory system may include some additional circuitry to repurpose the SEC circuitry for SECDED operations.

公开(公告)号：US10593384B2

公开(公告)日：2020-03-17

申请号：US16174782

申请日：2018-10-30

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm

IPC: G11C7/06 ,  G11C7/22 ,  G11C11/4076 ,  G11C7/10

Abstract: A memory device is provided. The memory device includes one or more memories and a connector operably coupled to the one or more memories and configured to receive signals including a first reference clock signal from a connected host. The memory device further includes circuitry configured to determine a frequency of the first reference clock signal. The circuitry can be configured to generate a second reference clock signal and to compare the first and second reference clock signals to determine the frequency of the first reference clock signal. The memory devices can further include circuitry configured to adjust one or more operating characteristics of the memory device in response to the determined frequency of the first reference clock signal.