公开(公告)号：US11748100B2

公开(公告)日：2023-09-05

申请号：US16824620

申请日：2020-03-19

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov

IPC: G06F9/30 ,  G06N3/08

CPC classification number: G06F9/30043 ,  G06F9/3001 ,  G06N3/08

Abstract: The present disclosure is directed to systems and methods for a Processing-In-Memory Device that is configured to perform dot product calculations. A sequence control may be used to store data in a memory array according to an allocation pattern. The cells of the memory array may correspond to array elements of the data. The sequence control may apply another array of data to groups of elements within the memory array using the allocation pattern to perform dot product calculations. The dot product calculations may be used, for example, to implement a layer in a convolutional neural network.

公开(公告)号：US20220383080A1

公开(公告)日：2022-12-01

申请号：US17334518

申请日：2021-05-28

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov

IPC: G06N3/063 ,  G06N3/04 ,  G06F9/38 ,  G06F9/30

Abstract: The disclosed embodiments are related to storing critical data in a memory device such as Flash or DRAM memory device. In one embodiment, a device comprising a plurality of parallel processors is disclosed, the plurality of parallel processors configured to: perform a search and match operation, the search and match operation loading a plurality of synaptic identifier bit strings and a plurality of spike identifier bit strings, the search and match operation further generating a plurality of bitmasks; perform a synaptic integration phase, the synaptic integration phase generating a plurality of synaptic current vectors based on the plurality of bitmasks, the synaptic current vectors associated with respective synthetic neurons; solve a neural membrane equation for each of the synthetic neurons; and update membrane potentials associated with the synthetic neurons, the membrane potentials stored in a memory device.

公开(公告)号：US11481334B2

公开(公告)日：2022-10-25

申请号：US17319002

申请日：2021-05-12

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Samuel E. Bradshaw ,  Kenneth Marion Curewitz ,  Sean Stephen Eilert ,  Dmitri Yudanov

IPC: G06F12/00 ,  G06F12/10 ,  H04L67/1097 ,  H04W84/04

Abstract: Systems, methods and apparatuses of distributed computing based on Memory as a Service are described. For example, a set of networked computing devices can each be configured to execute an application that accesses memory using a virtual memory address region. Each respective device can map the virtual memory address region to the local memory for a first period of time during which the application is being executed in the respective device, map the virtual memory address region to a local memory of a remote device in the group for a second period of time after starting the application in the respective device and before terminating the application in the respective device, and request the remote device to process data in the virtual memory address region during at least the second period of time.

公开(公告)号：US11474828B2

公开(公告)日：2022-10-18

申请号：US16592547

申请日：2019-10-03

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Samuel E. Bradshaw

IPC: G06F9/445 ,  G06F9/4401 ,  G06N3/08 ,  G06N3/04 ,  G06F12/06

Abstract: In a mobile device, processes of an application can be monitored and scored for initial data distribution. Specifically, a method can include monitoring processes of an application, and scoring objects or components used by the processes to determine placement of the objects or components in memory during initiation of the application. The method can also include, during initiation of the application, loading, into a first portion of the memory, at least partially, the objects or components scored at a first level. The method can also include, during initiation of the application, loading, into a second portion of the memory, at least partially, the objects or components scored at a second level. The objects or components scored at the second level can be less critical to the application than the objects or components scored at the first level.

公开(公告)号：US20220237039A1

公开(公告)日：2022-07-28

申请号：US17723846

申请日：2022-04-19

Applicant: Micron Technology, Inc.

Inventor： Sean Stephen Eilert ,  Ameen D. Akel ,  Samuel E. Bradshaw ,  Kenneth Marion Curewitz ,  Dmitri Yudanov

IPC: G06F9/50 ,  H04L41/0896 ,  G06F12/02 ,  G06F13/16 ,  G06F12/1009 ,  G06F12/08 ,  G06F12/1072 ,  G06F12/1036

Abstract: Systems, methods and apparatuses to throttle network communications for memory as a service are described. For example, a computing device can borrow an amount of random access memory of the lender device over a communication connection between the lender device and the computing device. The computing device can allocate virtual memory to applications running in the computing device, and configure at least a portion of the virtual memory to be hosted on the amount of memory loaned by the lender device to the computing device. The computing device can throttle data communications used by memory regions in accessing the amount of memory over the communication connection according to the criticality levels of the contents stored in the memory regions.

公开(公告)号：US11366752B2

公开(公告)日：2022-06-21

申请号：US16824621

申请日：2020-03-19

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov

IPC: G06F12/02

Abstract: A memory module system with a global shared context. A memory module system can include a plurality of memory modules and at least one processor, which can implement the global shared context. The memory modules of the system can provide the global shared context at least in part by providing an address space shared between the modules and applications running on the modules. The address space sharing can be achieved by having logical addresses global to the modules, and each logical address can be associated with a certain physical address of a specific module.

公开(公告)号：US11354134B1

公开(公告)日：2022-06-07

申请号：US17212551

申请日：2021-03-25

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov

IPC: G11C11/413 ,  G06F40/211 ,  G06F9/38 ,  G06F9/30 ,  G11C11/4094 ,  H03K19/1776 ,  H03K19/17728 ,  G11C11/408 ,  G06F15/78

Abstract: An example system implementing a processing-in-memory pipeline includes: a memory array to store a plurality of look-up tables (LUTs) and data comprising an input string; a logic array coupled to the memory array, the logic array to perform a set of logic operations on the data and the LUTs, the set of logic operations implementing a set of production rules of a context-free grammar to translate the input string into one or more symbols; and a control block coupled to the memory array and the logic array, the control block to control a computational pipeline by activating one or more LUTs of the plurality of LUTs, the computational pipeline implementing a parser evaluating the input string against the context-free grammar.

公开(公告)号：US20220156564A1

公开(公告)日：2022-05-19

申请号：US16951898

申请日：2020-11-18

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov

IPC: G06N3/063 ,  G06N3/04 ,  H04L12/751 ,  H04L12/759

Abstract: The present disclosure is directed to routing of data in a spiking neural network (SNN) that performs in-memory operations. To model a computer-implemented SNN after a biological neural network, the architecture in the present disclosure involves different memory sections for storing inbound spike messages, synaptic connection data, and synaptic connection parameters. Embodiments are directed to routing spike messages through various router-based topologies. For example, spike messages may be multicasted to target routers using address tables.

公开(公告)号：US20220067483A1

公开(公告)日：2022-03-03

申请号：US17005040

申请日：2020-08-27

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov

IPC: G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: The present disclosure is directed to pipelining operations of a spiking neural network (SNN) that performs in-memory operations. To model a computer-implemented SNN after a biological neural network, the architecture in the present disclosure involves different memory sections for storing inbound spike messages, synaptic connection data, and synaptic connection parameters (e.g., states). The section of memory containing synaptic connection data to identify matching inbound spike messages. In parallel, the section of memory containing synaptic connection parameters may be accessed to perform various neuromorphic calculations, synaptic plasticity and outbound spike message generation.

公开(公告)号：US20210303265A1

公开(公告)日：2021-09-30

申请号：US16836773

申请日：2020-03-31

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov

IPC: G06F7/544 ,  G06F3/06 ,  G06N3/08

Abstract: The present disclosure is directed to systems and methods for a memory device such as, for example, a Processing-In-Memory Device that is configured to perform multiplication operations in memory using a popcount operation. A multiplication operation may include a summation of multipliers being multiplied with corresponding multiplicands. The inputs may be arranged in particular configurations within a memory array. Sense amplifiers may be used to perform the popcount by counting active bits along bit lines. One or more registers may accumulate results for performing the multiplication operations.