公开(公告)号：US11594298B2

公开(公告)日：2023-02-28

申请号：US17750103

申请日：2022-05-20

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather ,  Randall J. Rooney

IPC: G11C29/42 ,  G11C29/44 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/406 ,  G11C29/00

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to monitor word line characteristics. In one embodiment, the memory device includes a memory array including a word line (e.g., a local word line) and a word line driver coupled thereto. When the memory device activates the word line driver, the memory device may generate a diagnostic signal in response to the word line voltage reaching a threshold. Further, the memory device may generate a reference signal to compare the diagnostic signal with the reference signal. In some cases, the memory device may generate an alert signal based on comparing the diagnostic signal with the reference signal if the diagnostic signal indicates a symptom of degradation in the word line characteristics. The memory device may implement certain preventive and/or precautionary measures upon detecting the symptom.

公开(公告)号：US11545199B2

公开(公告)日：2023-01-03

申请号：US17200233

申请日：2021-03-12

Applicant: Micron Technology, Inc.

Inventor： Gary Howe ,  Eric J. Stave ,  Thomas H. Kinsley ,  Matthew A. Prather

IPC: G11C7/22 ,  G11C7/10 ,  G06F13/40 ,  G11C8/10

Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.

公开(公告)号：US20220197740A1

公开(公告)日：2022-06-23

申请号：US17693990

申请日：2022-03-14

Applicant: Micron Technology, Inc.

Inventor： Randall J. Rooney ,  Matthew A. Prather

IPC: G06F11/10 ,  G11C29/44 ,  G11C11/406 ,  G11C29/42

Abstract: Methods, systems, and apparatuses for memory (e.g., DRAM) having an error check and scrub (ECS) procedure in conjunction with refresh operations are described. While a refresh operation reads the code words of a memory row, ECS procedures may be performed on some of the sensed code words. When the write portion of the refresh begins, a code word discovered to have errors may be corrected before it is written back to the memory row. The ECS procedure can be incremental across refresh operations, beginning, for example, each ECS at the code word where the pervious ECS for that row left off. The ECS procedure can include an out-of-order (OOO) procedure where ECS is performed more often for certain identified code words.

公开(公告)号：US20220004245A1

公开(公告)日：2022-01-06

申请号：US17479922

申请日：2021-09-20

Applicant: Micron Technology, Inc.

Inventor： Frank F. Ross ,  Matthew A. Prather

IPC: G06F1/3234 ,  G11C5/14 ,  G06F3/06

Abstract: The present disclosure includes apparatuses and methods related to power management in memory. Memory devices with multiple input/output ports may have the ports separately managed to transfer data from the various to a host or other components of the module based on certain power management signaling or constraints. For example, a memory device with multiple ports may be managed to transfer data to a host from one set of ports in response to power management (or other) signaling, and the device may be managed to transfer other data to another memory device in response to different power management (or other signaling). Power management may be done onboard a memory module with or without direction from a host. Power management may be performed by a dedicated integrated circuit. Data may be transferred from or between different classes of memory devices, using different ports, based on power management, e.g., criteria.

公开(公告)号：US11189327B2

公开(公告)日：2021-11-30

申请号：US16815999

申请日：2020-03-11

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather ,  Randall J. Rooney

IPC: G11C7/10 ,  G06F11/30 ,  G11C11/4093

Abstract: Memory devices, memory systems, and methods of operating the same are disclosed in which a memory device, in response to receiving a mode register read (MRR) command directed to one or more write-only bits of a mode register, reads data indicative of a status of the memory device about the memory device from one or more cells of a memory array of the memory device that are different from the write-only mode register. The data can include device settings, environmental conditions, usage statistics, metadata, feature support, feature implementation, device status, temperature, etc. The status information mode can be optionally enabled or disabled. The memory devices can include DDR5 DRAM memory devices.

公开(公告)号：US20210263685A1

公开(公告)日：2021-08-26

申请号：US17315532

申请日：2021-05-10

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  Thomas H. Kinsley ,  Matthew A. Prather

IPC: G06F3/06 ,  G11C7/10 ,  G11C11/4093

Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication. The device may transmit, from the first portion, a signal instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The signal may be provided at an ODT I/O terminal of the first portion coupled to an ODT I/O terminal of the second portion.

公开(公告)号：US20210209039A1

公开(公告)日：2021-07-08

申请号：US17207561

申请日：2021-03-19

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Matthew A. Prather

IPC: G06F13/16 ,  G06F5/06 ,  G06F1/3296 ,  G06F1/3234 ,  G06F1/3206

Abstract: Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.

公开(公告)号：US10976960B2

公开(公告)日：2021-04-13

申请号：US16212572

申请日：2018-12-06

Applicant: Micron Technology, Inc.

Inventor： Matthew A. Prather ,  Frank F. Ross

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/16 ,  G11C7/22

Abstract: A memory system is provided. The memory system includes a first memory device having a first latency corresponding to a first command and a second memory device having a second latency corresponding to a second command. The second latency differs from the first latency by a latency difference. The memory system further includes a host operably coupled to the first and second memory devices. The host is configured to send the first command to the first memory device at a first time, and to send the second command to the second memory device at a second time. The first time and the second time are separated by a delay corresponding to the latency difference.

公开(公告)号：US10950282B2

公开(公告)日：2021-03-16

申请号：US16540011

申请日：2019-08-13

Applicant: Micron Technology, Inc.

Inventor： Gary Howe ,  Eric J. Stave ,  Thomas H. Kinsley ,  Matthew A. Prather

IPC: G11C7/22 ,  G11C7/10 ,  G06F13/40 ,  G11C8/10

Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.

公开(公告)号：US20200278811A1

公开(公告)日：2020-09-03

申请号：US16290110

申请日：2019-03-01

Applicant: Micron Technology, Inc.

Inventor： Frank F. Ross ,  Matthew A. Prather

IPC: G06F3/06 ,  G06F12/02

Abstract: The present disclosure includes apparatuses and methods related to performing background operations in memory. A memory device can be configured to perform background operations while another memory device in a memory system and/or on a common memory module is busy performing commands received from a host coupled to the memory system and/or common memory module. An example apparatus can include a first memory device, wherein the first memory device can include an array of memory cells and a controller configured to perform a background operation on the first memory device in response to detecting a command from a host to a second memory device.