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公开(公告)号：US20150212882A1
公开(公告)日：2015-07-30
申请号：US14681564
申请日：2015-04-08
Applicant: Micron Technology, Inc.
Inventor： Troy A. Manning , Troy D. Larsen , Martin L. Culley
CPC classification number: G06F11/1068 , G06F3/061 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F3/0688 , G06F3/0689 , G06F8/44 , G06F11/108 , G06F2211/104 , G11C29/52
Abstract: The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory.
Abstract translation: 本公开包括用于物理页面，逻辑页面和码字对应的装置和方法。 许多方法包括将多个数据的逻辑页面的错误编码为码字的数量并将码字的数量写入存储器的多个物理页面。 数据的逻辑页数可以不同于存储器的物理页数。
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公开(公告)号：US08898424B2
公开(公告)日：2014-11-25
申请号：US13859502
申请日：2013-04-09
Applicant: Micron Technology, Inc.
Inventor： Troy A. Manning , Martin L. Culley , Troy D. Larsen
CPC classification number: G06F12/1045 , G06F12/0246 , G06F12/0292 , G06F12/1009 , G06F12/1027 , G06F2212/1004 , G06F2212/7201 , Y02D10/13
Abstract: The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.
Abstract translation: 本公开包括用于存储器地址转换的装置，系统和方法。 一个或多个实施例包括存储器阵列和耦合到阵列的控制器。 阵列包括具有多个记录的第一表，其中每个记录包括多个条目，其中每个条目包括对应于阵列中存储的数据段的物理地址和逻辑地址。 控制器包括具有多个记录的第二表，其中每个记录包括多个条目，其中每个条目包括对应于第一表中的记录的物理地址和逻辑地址。 控制器还包括具有多个记录的第三表，其中每个记录包括多个条目，其中每个条目包括对应于第二表中的记录的物理地址和逻辑地址。
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公开(公告)号：US20140317374A1
公开(公告)日：2014-10-23
申请号：US14255525
申请日：2014-04-17
Applicant: Micron Technology, Inc.
Inventor： Martin L. Culley , Troy A. Manning , Troy D. Larsen
CPC classification number: G06F3/0665 , G06F12/00 , G06F12/0246 , G06F12/0292 , G06F12/04 , G06F12/10 , G06F12/1027 , G06F12/1408 , G06F12/1475 , G06F2212/7201 , G06F2212/7202 , Y02D10/13
Abstract: The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range.
Abstract translation: 本公开包括用于逻辑地址转换的方法，用于操作存储器系统的方法和存储器系统。 一种这样的方法包括接收与LA相关联的命令，其中LA在LAs的特定范围内，并且使用对应于当写入与范围相关联的数据时跳过的物理位置的数量来将LA转换到存储器中的物理位置 的特定范围以外的。
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公开(公告)号：US20130227247A1
公开(公告)日：2013-08-29
申请号：US13859502
申请日：2013-04-09
Applicant: Micron Technology, Inc.
Inventor： Troy A. Manning , Martin L. Culley , Troy D. Larsen
IPC: G06F12/10
CPC classification number: G06F12/1045 , G06F12/0246 , G06F12/0292 , G06F12/1009 , G06F12/1027 , G06F2212/1004 , G06F2212/7201 , Y02D10/13
Abstract: The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.
Abstract translation: 本公开包括用于存储器地址转换的装置，系统和方法。 一个或多个实施例包括存储器阵列和耦合到阵列的控制器。 阵列包括具有多个记录的第一表，其中每个记录包括多个条目，其中每个条目包括对应于阵列中存储的数据段的物理地址和逻辑地址。 控制器包括具有多个记录的第二表，其中每个记录包括多个条目，其中每个条目包括对应于第一表中的记录的物理地址和逻辑地址。 控制器还包括具有多个记录的第三表，其中每个记录包括多个条目，其中每个条目包括对应于第二表中的记录的物理地址和逻辑地址。
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