公开(公告)号：US20210184044A1

公开(公告)日：2021-06-17

申请号：US17170082

申请日：2021-02-08

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Kamal M. Karda ,  Albert Fayrushin

IPC: H01L29/78 ,  H01L29/423 ,  H01L27/11582 ,  H01L29/51 ,  H01L27/11556 ,  H01L21/28 ,  H01L27/11597 ,  H01L29/792 ,  H01L27/1157 ,  H01L27/1159 ,  H01L29/66

Abstract: A programmable charge-storage transistor comprises channel material, insulative charge-passage material, charge-storage material, a control gate, and charge-blocking material between the charge-storage material and the control gate. The charge-blocking material comprises a non-ferroelectric insulator material and a ferroelectric insulator material. Arrays of elevationally-extending strings of memory cells of memory cells are disclosed, including methods of forming such. Other embodiments, including method, are disclosed.

公开(公告)号：US20210175246A1

公开(公告)日：2021-06-10

申请号：US16704938

申请日：2019-12-05

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Augusto Benvenuti ,  Haitao Liu ,  Xin Lan

IPC: H01L27/11582 ,  H01L29/10 ,  H01L27/11565 ,  H01L29/51 ,  H01L27/11573

Abstract: Some embodiments include a pillar which contains semiconductor material, and which extends primarily along a first direction. A cross-section through the pillar along a second direction orthogonal to the first direction is through the semiconductor material and includes a lateral periphery of the pillar configured as three-sided shape. Some embodiments include an integrated assembly having a vertical stack of alternating first and second levels. The first levels include conductive structures and the second levels are insulative. Channel-material-pillars extend through the vertical stack. Each of the channel-material-pillars has a top-down cross-section which includes a lateral periphery configured as three-sided shape of an equilateral triangle with rounded vertices.

公开(公告)号：US20210066328A1

公开(公告)日：2021-03-04

申请号：US16552257

申请日：2019-08-27

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Albert Fayrushin ,  Haitao Liu ,  Kirk D. Prall

IPC: H01L27/11556 ,  H01L27/11582

Abstract: Some embodiments include an assembly having a memory cell with an active region which includes a body region between a pair of source/drain regions. A charge-storage material is adjacent to the body region. A conductive gate is adjacent to the charge-storage material. A hole-recharge arrangement is configured to replenish holes within the body region during injection of holes from the body region to the charge-storage material. The hole-recharge arrangement includes a heterostructure active region having at least one source/drain region of a different composition than the body region, and/or includes an extension coupling the body region with a hole-reservoir. A wordline is coupled with the conductive gate. A first comparative digit line is coupled with one of the source/drain regions, and a second comparative digit line is coupled with the other of the source/drain regions.

公开(公告)号：US10803948B2

公开(公告)日：2020-10-13

申请号：US16183414

申请日：2018-11-07

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Augusto Benvenuti ,  Akira Goda ,  Luca Laurin ,  Haitao Liu

IPC: G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/16 ,  G11C16/04

Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a memory cell string having first, second, third, fourth, and fifth memory cells; access lines including first, second, third, fourth, and fifth access lines coupled to the first, second, third, fourth, and fifth memory cells, respectively, and a module. The first memory cell is between the second and third memory cells. The second memory cell is between the first and fourth memory cells. The third memory cell is between the first and fifth memory cells. The module is to couple the first access line to a ground node at a first time of a memory operation, couple the second and third access lines to the ground node at a second time of the operation after the first time, and couple the fourth and fifth access lines to the ground node at a third time of the operation after the second time.

公开(公告)号：US20190311756A1

公开(公告)日：2019-10-10

申请号：US16432250

申请日：2019-06-05

Applicant: Micron Technology, Inc.

Inventor： Ankit Sharma ,  Haitao Liu ,  Albert Fayrushin ,  Akira Goda ,  Kamal M. Karda

IPC: G11C11/22 ,  H01L27/105 ,  H01L27/11502

Abstract: A memory cell comprises channel material, insulative charge-passage material, programmable material, a control gate, and charge-blocking material between the programmable material and the control gate. The charge-blocking material comprises a non-ferroelectric insulator material and a ferroelectric insulator material comprising hafnium, zirconium, and oxygen. Other embodiments are disclosed.