公开(公告)号：US10909452B2

公开(公告)日：2021-02-02

申请号：US15357703

申请日：2016-11-21

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes

IPC: G06N3/08 ,  G06F1/3206 ,  G06K9/00 ,  G06F1/3287

Abstract: A device includes a state machine. The state machine includes a plurality of blocks, where each of the blocks includes a plurality of rows. Each of these rows includes a plurality of programmable elements. Furthermore, each of the programmable elements are configured to analyze at least a portion of a data stream and to selectively output a result of the analysis. Each of the plurality of blocks also has corresponding block activation logic configured to dynamically power-up the block.

公开(公告)号：US20200285604A1

公开(公告)日：2020-09-10

申请号：US16884302

申请日：2020-05-27

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown

IPC: G06F15/80 ,  G06F16/903 ,  H03K19/17728 ,  G06K9/00 ,  G06N5/00

Abstract: Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to feature cells, groups, rows, blocks, or any other arrangement of components of the pattern-recognition processor.

公开(公告)号：US10733508B2

公开(公告)日：2020-08-04

申请号：US15871660

申请日：2018-01-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David R. Brown ,  Harold B Noyes

IPC: G06N3/08 ,  G06K9/00 ,  G06N3/063

Abstract: A device includes a match element that includes a first data input configured to receive a first result, wherein the first result is of an analysis performed on at least a portion of a data stream by an element of a state machine. The match element also includes a second data input configured to receive a second result, wherein the second result is of an analysis performed on at least a portion of the data stream by another element of the state machine. The match element further includes an output configured to selectively provide the first result or the second result.

公开(公告)号：US10691964B2

公开(公告)日：2020-06-23

申请号：US15286229

申请日：2016-10-05

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  Michael C. Leventhal ,  Jeffery M. Tanner ,  Inderjit Singh Bains

IPC: G06K9/00 ,  G06K9/62 ,  G06F16/2455 ,  G06F9/448

Abstract: An automaton is implemented in a state machine engine. The automaton is configured to observe data from a beginning of an input data stream until a point when an end of data (EOD) signal is seen. Additionally the automaton is configured to report an event only when one and only one occurrence of a target symbol is seen in the input data stream.

公开(公告)号：US20200089416A1

公开(公告)日：2020-03-19

申请号：US16694584

申请日：2019-11-25

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B Noyes

IPC: G06F3/06 ,  G06N3/02 ,  G06F8/41

Abstract: A state machine engine includes a state vector system. The state vector system includes an input buffer configured to receive state vector data from a restore buffer and to provide state vector data to a state machine lattice. The state vector system also includes an output buffer configured to receive state vector data from the state machine lattice and to provide state vector data to a save buffer.

公开(公告)号：US10572414B2

公开(公告)日：2020-02-25

申请号：US16247244

申请日：2019-01-14

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  Stephen P. King

IPC: G06F13/28 ,  G06F13/38 ,  G06F13/40

Abstract: Disclosed are methods and devices, among which is a device that uses a memory map to identify whether functionality of the device should be implemented. The device may be coupled to a separate device, and, in some embodiments, the device may determine and provide a response of the device to requests from the separate device.

公开(公告)号：US10521366B2

公开(公告)日：2019-12-31

申请号：US16400739

申请日：2019-05-01

Applicant: Micron Technology, Inc.

Inventor： Debra Bell ,  Paul Glendenning ,  David R. Brown ,  Harold B Noyes

IPC: G06F12/10 ,  G06F13/12 ,  G06F13/40 ,  G06F13/28

Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

公开(公告)号：US10509995B2

公开(公告)日：2019-12-17

申请号：US15090305

申请日：2016-04-04

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown

IPC: G06N3/04 ,  G06F15/78 ,  G05B19/045 ,  G06N3/02 ,  G06F9/448

Abstract: A state machine engine having a program buffer. The program buffer is configured to receive configuration data via a bus interface for configuring a state machine lattice. The state machine engine also includes a repair map buffer configured to provide repair map data to an external device via the bus interface. The state machine lattice includes multiple programmable elements. Each programmable element includes multiple memory cells configured to analyze data and to output a result of the analysis.

公开(公告)号：US20190258592A1

公开(公告)日：2019-08-22

申请号：US16400739

申请日：2019-05-01

Applicant: Micron Technology, Inc.

Inventor： Debra Bell ,  Paul Glendenning ,  David R. Brown ,  Harold B Noyes

IPC: G06F13/12 ,  G06F13/40 ,  G06F13/28

Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.

公开(公告)号：US10339071B2

公开(公告)日：2019-07-02

申请号：US16192509

申请日：2018-12-10

Applicant: Micron Technology, Inc.

Inventor： Debra Bell ,  Paul Glendenning ,  David R. Brown ,  Harold B Noyes

IPC: G06F12/00 ,  G06F13/12 ,  G06F13/28 ,  G06F13/40

Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.